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HSPICE problem:Cascode stage with simple PMOS Current mirror

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nhaftad

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what`s wrong with this code?
in result of simulation 2 of MOSes are in linear region,why?
transistor parameters from Razavi`s book 0.5u process
why most of vdd voltage dropes across source - drain of PMOS of Current mirror?
Code: 
test
.MODEL N1 NMOS LEVEL=1
+VTO=0.7 GAMMA=0.45 PHI=0.9
+NSUB=9E+14 LD=0.08E-6 UO=350 LAMBDA=0.1
+TOX=9E-9 PB=0.9 CJ=0.56E-3 CJSW=0.35E-11
+MJ=0.45 MJSW=0.2 CGDO=0.4E-9 JS=1.0E-8

.MODEL p1 PMOS LEVEL=1
+VTO=-0.8 GAMMA=0.4 PHI=0.8
+NSUB=5E+14 LD=0.09E-6 UO=100 LAMBDA=0.2
+TOX=9E-9 PB=0.9 CJ=0.94E-3 CJSW=0.32E-11
+MJ=0.5 MJSW=0.3 CGDO=0.3E-9 JS=0.5E-8

M1 VX VG1 GND GND N1 L=0.5U W=25U
M2 VO VG2 VX GND N1 L=0.5U W=25U
M3 VO VY VDD VDD P1 L=0.5U W=75U
M4 VY VY VDD VDD P1 L=0.5U W=75U
CL VO GND 1PF
RS VG1 VINP 1K
VDD VDD GND DC 3V
VB1 VINM GND DC 0.88V
VB2 VG2 GND DC 1.04V
VIN VINP VINM AC 1mV
ID VY GND DC 0.1mA

.OP


result:
Code: 
 **** mosfets


 subckt                                              
 element  0:m1       0:m2       0:m3       0:m4      
 model    0:n1       0:n1       0:p1       0:p1      
 region       Linear     Linear   Saturati   Saturati
  id       131.7554u  131.7554u -131.7554u -100.0000u
  ibs        0.        -1.0264f    0.         0.     
  ibd       -1.0264f   -1.7786f   28.2214f    9.3686f
  vgs      880.0000m  937.3582m -936.8610m -936.8610m
  vds      102.6418m   75.2231m   -2.8221  -936.8610m
  vbs        0.      -102.6418m    0.         0.     
  vth      700.0000m  723.6865m -800.0000m -800.0000m
  vdsat    102.6418m   75.2231m -136.8610m -136.8610m
  vod      180.0000m  213.6717m -136.8610m -136.8610m
  beta       9.9755m    9.9485m   14.0682m   10.6775m
  gam eff  450.0000m  450.0000m  400.0000m  400.0000m
  gm         1.0239m  748.3545u    1.9254m    1.4613m
  gds      784.7315u    1.3904m   16.8439u   16.8439u
  gmb      242.8408u  168.1578u  430.5302u  326.7647u
  cdtot     21.1063f   23.7362f   22.8465f   22.6150f
  cgtot     49.1829f   50.3029f  112.2802f  112.0487f
  cstot     27.4513f   26.0546f   87.2881f   87.2881f
  cbtot    625.2053a  512.1458a    2.1456f    2.1456f
  cgs       27.4513f   26.0546f   87.2881f   87.2881f
  cgd       21.1063f   23.7362f   22.8465f   22.6150f
 

Hi
how did you choose your MOSFETs parameters W and L ?
the first step in designing a CMOS amplifier is designing bias network for mosfets ;
firstly choose appropriate Vov (over drive voltage) for each mosfet then then solve characteristic equation for them and find correct values for W
also you should choose bias voltages carefully
 

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