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[SOLVED] Multiple clock synthesis

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soloktanjung

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Hi,

I need help regarding multiple clock synthesis using Synopsys Design Compiler.

My design has 2 blocks, clk1 for block1 and clk2 for block2. The clocks are independent each other and generate from different source from outside chip. How can I synthesis the design?
I tried to synthesis it by creating 2 clocks, setting the constraint for both clock independently, but the report_timing showed both clocks are dependent each other, which is launch clock is clk1 and captured clock is clk2.

I dont know it is correct or not. Can someone verify me please?

This is part of the report_timing:

Code: 
  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  clock clk1 (rise edge)                                   27.00      27.00
  clock network delay (ideal)                             2.50      29.50
  ...
  ...
  ...
  data arrival time                                                 32.70

  clock clk2  (rise edge)                                  28.00      28.00
  clock network delay (ideal)                             2.50      30.50
  ...
  ... 
 clock uncertainty                                      -0.20      30.30
  library setup time                                     -0.17      30.13
  data required time                                                30.13
  --------------------------------------------------------------------------
  data required time                                                30.13
  data arrival time                                                -32.70
  --------------------------------------------------------------------------
  slack (VIOLATED)                                                  -2.57


Thank you in advance.

Hairo
 

It means you have a data path going from a flip-flop clocked by clk1, to a flip-flop clocked by clk2.

If the clocks are asynchronous and you don't want to time these paths, do:

set_clock_groups -async -group clk1 -group clk2

or

set_false_path -from clk1 -to clk2
 
I want to synthesize a Clock domain crossing design. Do i need to set a false path from clk1 to clk2 as explained by jbeniston?
 

I used a FIFO with 2 clocks for clock crossing domain. So I think yes you need to set it false.
 

Hi

Could you share your FIFO design with multiple clocks including the synthesis script.

I'll appreciate.

The email address is sent to you via personal message.
 

If u know the two clocks are totally independent then u better set it as false paths and use FIFO to design the domain crossing.

If they are coming from a same clock source, but diff generators here also u have to check to see the phases of the clocks are same or not. If not same then also u might need FIFO.

Please let me know if there is any mistake in my above statement.

Thanks
 

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