Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

help on THD of the Capacitive Reset Gain Circuit

Status
Not open for further replies.
A

allennlowaton

Full Member level 5
Joined
Oct 5, 2009
Messages
247
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,298
Location
Taiwan
Activity points
3,066
Good day EDA fellows,

I badly needed your help regarding this one.
Below is the capacitive-reset gain circuit.


This is also the frequency response of my op-amp.


Shown below are the THD simulation results;



My concerns now are these: a) why the THD values for inputs at 1k and 100k are so big?
b) why the THD values for these input conditions (10k at 1MHz clock, 1k at 100k clock) are significantly lower?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top