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doubts in vhdl coding

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M.Shobana

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hi sir/madam.............
here i have attached my vhdl coding i am facing some problem regarding size allocation of 'd' and 'q'.so please verify my coding and mention me if any errors found in this coding...


Code:
Library ieee;
Use ieee.std_logic_1164.all;
entity fsm is
       Port(clk,rst:in bit;d:out std_logic_vector(89 downto 0);q1:inout std_logic_vector(2 downto 0);q2,q3:inout std_logic_vector(5 downto 0);q4,q5,q6,q7:inout std_logic_vector(6 downto 0);q8,q9,q10,q11:inout std_logic_vector(7 downto 0);q12,q13,q14,q15:inout std_logic_vector(8 downto 0);x:std_logic_vector(14 downto 0));
end fsm;
architecture behave of fsm is
Type state_type is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,sin);
signal next_state,Ps_state:state_type;
Begin
         Process(clk,rst)
         begin
             if rst='1' then
                  Ps_state<=s0;
             elsif clk'event and clk='1' then
                 Ps_state<=next_state;
            end if;
end process;
process(x,ps_state)
    begin
case ps_state is 
  when s0=>
         if x(0)='0' then
               next_state<=s1;
               q1<="001";
            else
               next_state<=sin;
             q1<="000";
   end if;
When s1=>
         If x(1)='0' then
               next_state<=s1;
               q2<="010";
         else
               next_state<=sin;
      q2<=q1 & "000";
   End if;
When s2=>
         If x(2)='0'  then
               next_state<=s1;
               q3<="011";
         else
               next_state<=sin;
            q3<=q2 & "000";
   end if;
When s3=>
         If x(3)='0' then
               next_state<=s1;
               q4<="1000";
       else
               next_state<=sin;
q4<=q3 & "000";
   end if;
When s4=>
         If x(4)='0' then
               next_state<=s1;
               q5<="1001";
       Else
               next_state<=sin;
q5<=q4 & "000";
   end if;
When s5=>
         If x(5)='0'  then
               next_state<=s1;
               q6<="1010";
       Else
               next_state<=sin;
      q6<=q5 & "000";
   end if;
When s6=>
         If x(6)='0' then
               next_state<=s1;
               q7<="1011";
       else
               next_state<=sin;
           q7<=q6 & "000";
   end if;
When s7=>
         If x(7)='0' then
               next_state<=s1;
               q8<="11000";
       Else
               next_state<=sin;
q8<=q7 & "000";
   end if;
When s8=>
         If x(8)='0'  then
               next_state<=s1;
               q9<="11001";
       else
               next_state<=sin;
q9<=q8 & "000";
   end if;
When s9=>
         If x(9)='0'  then
               next_state<=s1;
               q10<="11010";
       else
               next_state<=sin;
             q10<=q9 & "000";
   end if;
When s10=>
         If x(10)='0' then
               next_state<=s1;
               q11<="11011";
       else
               next_state<=sin;
            q11<=q10 & "000";
   end if;
When s11=>
         If x(11)='0' then
               next_state<=s1;
               q12<="111000";
         else
               next_state<=sin;
            q12<=q11 & "000";
   end if;
When s12=>
         If x(12)='0' then
               next_state<=s1;
               q13<="111001";
        else
               next_state<=sin;
              q13<=q12 & "000";
   end if;
When s13=>
         If x(13)='0' then
               next_state<=s1;
               q14<="111010";
        else
               next_state<=sin;
q14<=q13 & "000";
    End if;
When s14=>
         If x(14)='0'  then
               next_state<=s1;
               q15<="111011";
       else
               next_state<=sin;
          q15<=q14 & "000";
    End if;
When sin=>
          next_state<=s0;
 end case;
d<=q1 & q2 & q3 & q4 & q5 & q6 & q7 & q8 & q9 & q10 & q11 & q12 & q13 & q14 & q15;
End process;
End behave;
 
Last edited by a moderator:

Since you are concatenating all the q" values to signal "d". "d" should have size to hold all the q values. Add all the bit size of q as 3++6+.... and put the size for d
 

In addition, there are also assignments of wrong bit length to various qx signals. In other words, you seem to have some problems with counting.

I guess, there's also a general conceptual problem with your code. You have concatenations like this
q5<=q4 & "000";
But q4 and q5 are defined with same bit length. Are you sure to know what you want to achieve?
 

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