How to import gate-level netlist into ECS ?

ecs schematic

When Verilog/VHDL design(s) are synthesized into the gate-level netlist, how do you import the netlist into ECS schematic environment ?

Because I am doing the digital design, and I use the ECS schematic to do the module interconnection. In order to integrate the whole design into the same database, I hope to translate the gate-level netlist into ECS format.

Anybody can help me ?
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I know the $ynopsys 33a (1998.02 version) has the ability to write the Verilog gate-level netlist into ECS schematic(s).

But how to do this in the later versions, such as 2000.05, 2001.08, and 2002.05.
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For V!ewDraw.
P0werView/W0rkView can read-in EDIF schematic, and most logic synthesizer(s) are able to export this format. So there is less issue.

But for ECS, I have checked the current version 5.11, it still does not have this feature.

ecs netlist

some taiwan design house still use ECS old version to do their asic design job ,(maybe for the lib reason)
so i create workview format and print it into pdf , they make ecs sch by HAND !
anyway , the ecs is a very good sch tools , a wonderful win16 platform tool.

the ECS in xilinx ise is the newer version of ECS.

what is ecs schematic format

As i know , ecs can't import these post-synthesis netlist ! You can use Novas debussy !

Write EC$ schematic(s) out ...

Firstly, I am wondering that when design comes to ~million(s) gate count, how it's possible to draw the gate-level schematic(s) by hand ?

And every time, when the Verilog code(s) have been modified, the related gate-level schematic(s) are needed to be drawn again ...and again

If the design is not quite large and does not have much to change, then it tolerable to draw it by hand and do ECO later.
(But it is still time-consuming !)

By the way, I would like to ask "Already have ViewDr@w's schematic database, why need to port it into C0hesion/ECS' schematic format ?"
I really don't understand.
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I think maybe I need to state my request more clearly.
I'm looking for the software/tool which can automatically translate
the Verilog gate-level netlist(.v) into ECS' schematic(.sch) file.

Only because I hope the whole design database can be integrated
into the same environment. And the advantage of translating into C0hesion/ECS is I can export different netlst(s), such as Verilog and SPICE later.
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ps:
It's not my purpose to just "viewing" the gate-level schematic(s).
If I want to do so, then Debuss$y or Design @nalyzer can help me.

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I use ECS241 , 446 for some years, I think your question will have no answer ! Think about millions gates netlist , in ecs , you must split it to thousands pages , it no possible !

Next year ECS v6.0 can translate edif to
sch & sym .
Synoppsys can edif out to ECS v6.0 environment edit your ECO circuit.