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Decimation filter wuery in Sigma delat adc

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juneja

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Okay... so I know that there are a lot of posts on this forum for decimation filters: but I am feeling more confused. I have designed a sigma delta adc, with an 18 bit output. Now I want to design a decimation filter for the same. The question that puzzles me out is: HOW do I get a 18 bit, parallel output from a decimation filter? All architectures seem to be implementing single bit outputs: rather often are averaging the adc output to give an equivalent quatized output: analog, as it seems to me. Please help me. I am in dire need of this.

Thanks a lot!
 

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