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A problemin Converting Verilog(Gate Level)to Spice Netlist(Standard Cells) with HSIM

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Oveis.Gharan

Oveis.Gharan

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I convert my synthesized veriolg code into spice netlist but i have a problem.
Every Cell (subcircuit) has its own VDD and VSS net name, but i want to have the netlist which has unique supply name for power supply net name.

This is a sample of output converted netlist:
Code: 
.
.
.
XU9 PA n9 X1[0] VDD_dummy47 VSS_dummy48 NAND2_X1
XU8 PA n8 X1[1] VDD_dummy49 VSS_dummy50 NAND2_X1
XU7 PA n7 X1[2] VDD_dummy51 VSS_dummy52 NAND2_X1
XU6 PA n6 X1[3] VDD_dummy53 VSS_dummy54 NAND2_X1
.
.
I want all the cells VDD and VSS be connected to the global supply net.
Is there anyone can suggest a solution?

Thanks in advance.
Best Regards.
Oveis.
 

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