Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

dc_topo interconnect estimation versus icc interconnect estimation while placement

Status
Not open for further replies.
S

sudheerkolamala

Newbie level 4
Joined
Aug 10, 2010
Messages
5
Helped
7
Reputation
14
Reaction score
6
Trophy points
1,283
Location
india
Activity points
1,305
hi guys,

i observed in my design that there is significant difference between syn and place WNS and TNS.
why does syn has higher numbers of WNS,TNS compared to place.
DC_topo does some coarse placement for rc estimation,
1.does dc do more buffering than icc placement?
2.is the rc estimation more pessimistic in dc than ICC?

thanks,
sudheer
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top