Develop a IP Core for Memory Generator [Xilinx]

Hi,

Im doing this project for my FYP and selected this.

Develop a IP Core for Memory Generator [Xilinx]

To use VHDL and develop an IP that will be able to generate different types of memories such as ROM, single, simple dual and dual-port random access memories and SRL 16-based memories. Also these memories will support a range of data depth from 16 -65,536 words and data width ranging from 1- 1K bits. The newly developed IP has to be benchmarked with the Xilinx IPs for their performance with respect to delay and other significant parameters.

From what I understand, im supposed to make an IP Core like the one done by Xilinx and test against it.

Any ideas as to how I can proceed and read up on this?
Everywhere I type IP Core and google I get "how to implement it" not how to make one.

Any advice would be highly appreciated.

Thnx in advance. :-D

one of my methods ,a simple approach
you can try to develop a core generator in some scripting language like

tcl

perl


python is of course another great option.


And lots of resources are available for Tcl ,you can create very impressive GUI as Well

---------- Post added at 10:24 ---------- Previous post was at 10:19 ----------

h**p://coretml.sourceforge.net/

Coretml is another option

CoreTML framework was created primarily as an IP core generator platform for the design and deployment of semiconductor IP cores on a register transfer level (RTL) using hardware description languages (HDL)

Thnx

Any advice on how I can start coding with VHDL for
ROM, single, simple dual and dual-port random access memories and SRL 16-based memories.
Also any parameters that I can try changing after making the code and for testing.

Im thinking of the whole GUI thing later on if all goes well.

akeedthe said:

Thnx

Any advice on how I can start coding with VHDL for
ROM, single, simple dual and dual-port random access memories and SRL 16-based memories.
Also any parameters that I can try changing after making the code and for testing.

Im thinking of the whole GUI thing later on if all goes well.

Click to expand...

I think , XST user manual Recommended Coding style will be very useful

h**p://www.xilinx.com/support/documentation/sw_manuals/xilinx11/xst.pdf

And there is also a recommended Coding Style for Altera Quartus.

How can I measure latency when testing these memorys?

Can someone answer;

Why would it be essential to test diff memory vhdl modules on diff Xilinx FPGA boards? What would this make one understand by doing so?

different chips may have slightly different memory architectures. So testing it across the range will show you if it is fully compatable.

very useful post

I submitted my project proposal last week, so now its onto the "hard" part

Anyway, I thought of first taking the single port RAM and firstly coming up with it using Xilinx own IP. Any thoughts on how to proceed?

Yes it's a good Idea to begin with a Single port RAM

Ive been trying to get the Single port RAM working - using Xilinx core firstly.

COMPONENT spram16x4
PORT (
a : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;

Im finding it a bit of a problem to make the address shift along - I think im supposed to use a counter, but as there are no read n write address buffers its a bit confusing for me.

Can the top level have ports that include these even tho the core gen doesnt give them.

Thnx