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[help]how to do the constraint for mux or gated clock in DC?

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xigu

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gated clock mux

I need synthesis a project with some gate or mux clock,
for example:

clk1 = clk1_en & clk_tx;
//clk_en1 comes from other clock domain: clk_pci
clk2 = state? clk_pci : clk_rx;

how set constraint ?
i try use set_case_analysis
or create_generated_clock, but not set right.

thanks
 

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