synthesized netlist as input for power

We can extract power by synthesis tool. Should the gate level synthesized netlist generated by synthesis tool be taken as an input for estimation of power? Can we estimate the power of that gate level netlist corresponding to different corners of the same library by directly taking generated gate level netlist as the input for power estimation where the gate level netlist has been synthesized at a different corner for the same library?

yes, you can. Power estimation tool takes netlist and power info for each gate from library. Gate level netlist does not depens on corner, but library is for specific corner. Just changing library, you can estimate power for different corners. It can be done in different sessions, or by using multi-scenario possibility of Synopsys-PX.

But gate level synthesis was done from a library of different corner. Now to estimate power in different corner we are using another library relating to the required corner. Does it gurantee that all the type of gates that are there in the gate level netlist will also be present in this library that will be used for power estimaton.

To ask the same question in different way: Is that the foundry keeps the kind of cells and number of cells exactly same when it provides the library at different corners?

---------- Post added at 11:15 ---------- Previous post was at 11:10 ----------

Second question o you want to mean that for estimating power at different corners each time only one library for a specific corner (at which the power is required to be estimated) should only be present and other libraries should not present at all there?

multiple corner multiple mode analysis in PT should be a common feature now. Just refer to the manual on how to do it. If the foundry still wanna make money it would not make the gate types different between its different characterization corners.

Library provider (library developer) is using the same set of gates for characterizing them in several different corners, so you can use the same netlist and only one corner or (in multi-scenarion mode) some corners for analysing time/power for different operating conditions. Another story, that one library provider may develop some libraries (each of them characterized for several corners) (one is high-speed, one in high-density etc), and each of these libraries may have different set of gates. But, in such case, the names of these libraries will be different.

Regarding how many corners you should use: in a simple mode you may use only one corner for estimating power in this corner, in multi-scenario mode you may use some corners for estimating power in each of these corners. The same true and for timing estimation.

iamluqi

I am using synthesis tool for power estimation and not PT.

Synthesis tool (Synopsys DesignCompiler have possibility of multi-scenarion mode). In case, you are using another synthesis tool, re-run power estimation for each corner, you want.

oratie

Do we need to read the SDC first and then to set toggle rate on every net to estimate power. Or. is it sufficienent to set toggle rate on every net instead of reading SDC?

You need SDC, at least in order to define clock. It also may contains capacitance load on output ports etc. After that, the tool will calculate timing for your netlist, define input transitions on each input pins of each gate. After that, you will define switching activity (toggle rate). And after that the tool will calculate power. You can see in the synopsys library, that internal power for each gate usually depends on input transition and output capacitance.

oratie
Why do we need to define clock? We put toggle rate and that toggle rate is also provided to each net. So when we assign it to each net then the clock pins also automatically assigned the toggle rate. So we need not to define clock through sdc. But I agree capacitance load on output ports and set_deriving cell at input ports are necessary.

What do you mean by "tool will calculate timing for your netlist, define input transitions on each input pins of each gate"? Here we are trying to estimate power. Why is timing analysis necessary and why will the tool do timing analtsis? What do you mean by 'define input transitions on each input pins of each gate'? How will the tool define nput transition? We are providing a togggle rate for every nets. So, why is necessary to define input transition to each input pin? What is the command in dc to define input transtion to each pin?

You may define toggle rate as number of toggles in time unit, or as number of toggles in clock period. In first case, SDC is not needed, you are right.

BUT, let's open synopsys library which contains timing/power data for each of your gates. Usually, you will see, that leakage power is represented by one number (no dependency on transition/capacitance, possible dependency on input pins states). For internal power you (usually, syn library syntax permit several different formats) probably find some 2-D tables, where the one index is input_pin_transition and the second is output_pin_capacitance. Do you agree, that amount of internal(dynamic) power, that CMOS cell consume is dependent on input pin transition?

So, now we need to calculate for each input pin of each gate in your netlist the transition time. DC will calculate these numbers by report_timing or update_timing commands. And for these command, SDC is must. How it calculate transition time - please, read the books. It is not so complicated.

I know and also agree that amount of internal(dynamic) power, that CMOS cell consume is dependent on input pin transition. That is the reason we are providing toggle rate to each net. Depending upon the toggle rate that we provide different gates will show different power. Why do we need synthesis tool to read the SDC? However, I am using RTL Compiler.