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how to reduce cell leakage power in large design

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gpremala

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how to reduce cell leakage power in large design
 

Use HighVt library cells (cells with high voltage threshold transistors) in timing non-critical paths. Use low voltage. Use power gating method (switch-off supply for currently unused modules). Use LowPower foundry process (they increase voltage threshold for CMOS). Use multi-channel libraries.
 
There are many ways to reduce the leakage power

below are the methods for reducing it
1. Using Multi Vt cells.
2. Power Gating using isolation cells and retention registers.
3. Multi voltage using level shifters, isolation cells and retention registers.
4. Reducing the power supply voltage.
5. Body biasing
 

what type of constraints should i give for body biasing in design compiler
 

if part of design do not use in some application board,you can chose low power methedology to power off these parts to redues leakage power
 

what type of constraints should i give for body biasing in design compiler
reserve a separate supply rail for body. Generally std cell lib provides such an option
 

in general there are a few type of MOS transistor . for example in 90nm process from TSMC you can find Standard or General, Low-power, Low-voltage, High-voltage MOS transistors. if you need low power design you should use LP MOS transistor, this type transistors have a high Vt and low leakage currents, but need to keep in mind that LP transistors are low speed. this is one way to decreasing power consumption. and please remember you CAN'T use different type transistor (LP, G etc ) in same design, because they have a difference core supply voltage, and in physical design you need to separate different transistor from each others with guarding which will increase the area.
 

You should also weight leakage power optimization more heavily in your synthesis and automated layout design tools. All tools have to make trade-offs between dynamic power, leakage power and chip speed. Make sure you read the manuals about the low power features available with your tools.

Also, you should shrink your chip size as much as possible. Smaller size will result in lower total interconnect length which will lower parasitic leakage.

Check what other low power features your foundry has. In particular, you are interested in deep n-well isolation or SiO2 backside insulation.
 

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