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negative bias to pmos.

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wafi_zuhdi

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hi can anyone tell me what happen if we put negative voltage to a PMOS gate. let say for example, i'm using a 3v supply (0 - 3v) and maybe -2v at the pmos input. i assume that a pmos will still work as normal, drawing more current since vgs will be bigger. is there a limit to this? breakdown voltage maybe?
 

The max Vgs is specified in the datasheet (usually around 20v) , as long as Vgs is lower than this voltage there is no problem.

The mosfet gate doesn't draw current like the base of the transistor, there is just a gate capacitance that needs to be charged in order for the mosfet to conduct.

Alex
 

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