billmcgill2
Newbie level 2
Hi guys, I have a quite fundamental question here:
We know that the SysGen based design flow is much simpler and more efficient than the traditional HDL based design flow for FPGAs nowadays,
why there are still a lot people that are endeavoring in the HDL based design?
Thanks a lot.
We know that the SysGen based design flow is much simpler and more efficient than the traditional HDL based design flow for FPGAs nowadays,
why there are still a lot people that are endeavoring in the HDL based design?
Thanks a lot.