Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Mealy vs Moore vs Medvedev FSM in VHDL

Status
Not open for further replies.

shaiko

Advanced Member level 5
Joined
Aug 20, 2011
Messages
2,644
Helped
303
Reputation
608
Reaction score
297
Trophy points
1,363
Activity points
18,302
Hello All,

I have a simple question regarding the following VHDL codes:

-- first code
when state_0 =>
if input = '1' then
output <= '0';
end if;
----------------------

-- second code
when state_0 =>
output <= '0';
if input = '1' then
next state <= state_1;
end if;

when state_1 =>
output <= '1';
---------------------

from what I understand, the first code represents a MEALY FSM while the second is MOORE.

Is this correct?
 

Yes
You forgot the next state in the first code.
 
  • Like
Reactions: shaiko

    shaiko

    Points: 2
    Helpful Answer Positive Rating
what about a Medvedev FSM (Full Moore)?
can someone explain how it differs from the two examples above?
 

Do not fill your head all the scientific stuff. Isolation of the trigger circuitry on a series of 74 - comfort and versatility of a scheme to separate IC.
on HDL is not required.
 
  • Like
Reactions: shaiko

    shaiko

    Points: 2
    Helpful Answer Positive Rating
I'm not sure, if the term Medvedev FSM is commonly used, but this design differs from Mealy/Moore by having registered outputs. Respectively the outputs are registered state bits. In my opinion, it's the natural way to design a state machine.
 

Hello FvM,

Unless the application requires a low latency response, I write the FSM in a single process.
This way, the outputs are always registered
 

Unless the application requires a low latency response, I write the FSM in a single process.
This way, the outputs are always registered.
In terms of theoretical prototypes, this operation seems nearest to the Medvedev type.
 
  • Like
Reactions: shaiko

    shaiko

    Points: 2
    Helpful Answer Positive Rating
Do you see any advantages in using a MOORE FSM instead of a registered output MEALY?
 

I don't see a big practical difference and won't think about the principle nature when designing FSMs. In so far, I agree with treqer. In some cases it may be interesting to know, if and how many additional registers are created by the registered outputs and how they behave in case of timing violations.

The Medvedev prototype I've seen in literature has the output signals identical with state variable bits. In a VHDL design, the state variable is preferably an enumeration. You would write separate assignments for the registered output signals and leave it to the synthesis tool to merge them with the state variable bits if possible. In other words, you don't exactly know, if additional registers are generated when only looking at the code. In the "registered ouput " Mealy case, the right hand side of output assignments is different from state variable assignments, so additional registers are created anyway.
 
  • Like
Reactions: shaiko

    shaiko

    Points: 2
    Helpful Answer Positive Rating
I don't see a big practical difference and won't think about the principle nature when designing FSMs. In so far, I agree with treqer. In some cases it may be interesting to know, if and how many additional registers are created by the registered outputs and how they behave in case of timing violations.

The Medvedev prototype I've seen in literature has the output signals identical with state variable bits. In a VHDL design, the state variable is preferably an enumeration. You would write separate assignments for the registered output signals and leave it to the synthesis tool to merge them with the state variable bits if possible. In other words, you don't exactly know, if additional registers are generated when only looking at the code. In the "registered ouput " Mealy case, the right hand side of output assignments is different from state variable assignments, so additional registers are created anyway.

If thats what medvedev is, there used to be a guy who worked here who did exactly that - the state encodings were the outputs. It was done quite neatly, using dont cares ( '-' ) where he didnt care what the output was. To be honest, although it looks neat, I think it can be a bit harder to follow for a 3rd party rather than a good enumeration.
 

To be honest, although it looks neat, I think it can be a bit harder to follow for a 3rd party rather than a good enumeration.
I see a reasonable application of the true Medvedev type (outputs = state variable bits) only with very small CPLDs where you need to minimize the register count. In fact, I have designed FSMs this way without knowing the name.

In FPGA design with VHDL, one should use enumerated states. A one-process Moore FSM with registered outputs is however rather close to the Medvedev design, which was shaiko's point, if I understand right.
 

I agree.
If a Medvedev FSM is what you suggest it is I wouldn't bother using it.

Also, I usually avoid the MOORE model. Coding wise, it's very restricting and results in a larger number of states.
On the other hand - MEALY is much more versatile. It enables us zero latency response (two processes) or fully synchronous logic with registered outputs (one process). This comes with the bonus of a more compact code with less states.
I see no reason not to use it all the time...

Anyone disagrees?
 

I agree.
If a Medvedev FSM is what you suggest it is I wouldn't bother using it.

Also, I usually avoid the MOORE model. Coding wise, it's very restricting and results in a larger number of states.
On the other hand - MEALY is much more versatile. It enables us zero latency response (two processes) or fully synchronous logic with registered outputs (one process). This comes with the bonus of a more compact code with less states.
I see no reason not to use it all the time...

Anyone disagrees?
Yes, I disagree...

The definition of a Mealy state machine is that there is at least one path from input to output without a register (zero latency response). This means that a Mealy state machine must be implemented with two processes, one synchronous and one combinatorial.

If you do a fully synchronous state machine in one process, it is not a Mealy machine.
 

The definition of the MEALY model that I'm familiar with, describes it as an FSM with outputs that are a function of inputs and current state.
 

I agree with the state machines you prefer.
It is just a terminology question.

I agree that both the state machines you prefer are derivatives of the Mealy. We can call the synchronous version for "Mealy plus output registers".

A "strict Moore" machine is almost useless today since you don't want logic after the registers.

I also agree with earlier postings that the best is to forget the Mealy/Moore terminology. It is from a time when you had to describe a design with a minimum number of registers.

Don't let your VHDL code be restricted by ancient terminology!
 
Last edited:
  • Like
Reactions: shaiko and FvM

    FvM

    Points: 2
    Helpful Answer Positive Rating

    shaiko

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top