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Process Variations and Timing effects

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vid31

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Hi

I am using TSMC 65nm library.

There are two worst case library(SS).
One is having following conditions
Operating Condition Name : WCCOM
Process : 1.00
Temperature : 125.00
Voltage : 0.90
and other having these conditions
Operating Condition Name : WCCOML
Process : 1.00
Temperature : -40
Voltage : 0.90
Here, only difference is in temperature.

So, anywone tell me which one will give me more delay i.e. worst of them for set up violation?
and why?

Regard & Thanks,
Vid31
 

Hi,
I did and it shows that low temperature lib has more delay.

But as far as I know at high temperature,due to decrease in mobility delay will be more.

So,Isn't this result contradictory?
Please help me,


Regard & Thanks,
Vid31
 

have u heard abt temperature inversion.
This is applicable for designs at lower nodes say below 65nm.

Since increase in temperature at lower nodes makes the atoms in path gain more energy and thus mobility of the atoms increases and thus causes less delay.

i guess this is what ur seeing here.
 
grouth of Vth at the low temperatures will increase delay, while mobility increasing produce an opposite effect. Question is where it will ballance each other.
 

WCCOML is a max leakage power corner. It must be used for estimating leakage power of your design. Regarding temp inversion - it depends on the design - sometime you can observe it, sometime - no. So, to check timing - will be better to use both of these libs, to check leakage power - use WCCOML
 

As far as I know, the inversion occurs only when the supply voltage is low.
In normal case with standard voltage, you should not expect inversion to happen.

pavanks said:
have u heard abt temperature inversion.
This is applicable for designs at lower nodes say below 65nm.

Since increase in temperature at lower nodes makes the atoms in path gain more energy and thus mobility of the atoms increases and thus causes less delay.

i guess this is what ur seeing here.
Click to expand...
 
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