limjm
Newbie level 1
I made a T-flipflop by using RTL_compiler and Encounter, export it to GDSII file, and run DRC on virtuoso.
However, this layout cannot pass the DRC. This is because the distance of standard cells are too close, so it cannot satisfy minimum distance between P-well and N-well.
In addition, the via in power routing are not made on virtuoso like below.
Do you know why and how I can fix it?
Thank you
However, this layout cannot pass the DRC. This is because the distance of standard cells are too close, so it cannot satisfy minimum distance between P-well and N-well.
In addition, the via in power routing are not made on virtuoso like below.
Do you know why and how I can fix it?
Thank you
