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VHDL Manchester Encoder Serial input , Serial Output Moore State

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maldini

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i been trying to do a Manchester Encoder using vhdl, As MOORE STate, This is my code and for a reason i am not getting it right. i suppose to get an output a 01 for input of '0' and output of 10 for input of '1'.



library ieee ;
use ieee.std_logic_1164.all;

entity SM is
port( input: in std_logic;
clock: in std_logic;
reset: in std_logic;
output : out std_logic);
end SM;
architecture Behavioral of SM is
signal next_state, current_state: std_logic_vector (2 downto 0);

begin
process(Reset,current_state)
begin

if reset = '1' then
next_state <= "000";

elsif current_state="000" then
if (input='0') then
next_state<="001"; -- output should be 01
else
next_state<="010";-- output should be 10

end if;

elsif current_state="001" then -- in=0 out 01
output<='0';
next_state<="011";
elsif current_state="011" then
output<='1';
next_state<="000";


elsif current_state="010" then -- in 1 out 10
output<='1';
next_state<="100";
elsif current_state="100" then
output<='0';
next_state<="000";


end if;
end process;

process(clock, next_state) -- update current state
begin
if (clock'event and clock = '1') then

current_state <= next_state;

end if;
end process;
end behavioral ;
 

you need to assign output in all branches of your state transition process. Without it, output will be latched (which is bad).

And usually with a 2 process state machine, the reset is done in the clocked process, not the asynchronous process.
 

And usually with a 2 process state machine, the reset is done in the clocked process, not the asynchronous process.
Yes, for the usual asynchronous reset. The present code is implementing a synchronous reset, not so bad at all.

The problem is in the FSM state design however. It's going through three states for an input signal of 0 or 1, so it can hardly implement manchester encoding. You don't have any data clock, so the system clock will work as output clock. Is that what you want?

I suggest to sketch a waveform scheme before writing any FSM code. I would also prefer an enumeration for state variable, it improves readability and is required by some synthesis tools for optimal processing.
 

so what do u suggest, can anyone help me with code, or tell me where do i need to change. all i need is to encode a serial data in manchester . i know the output suppose to take 2 cycle as it convert the 1 bit to 2 bit.
 

How about the data clock? In my view, a Manchester encoder is simply toggling between two states, output data and output inverted data, involving one flip-flop and an EXOR gate.
 

But i am required to use State machine Moore state, can i still do that?

---------- Post added at 12:30 ---------- Previous post was at 12:06 ----------

i chjange the code, is that what u were talking about


library ieee ;
use ieee.std_logic_1164.all;

entity SM is
port( input: in std_logic;
clock: in std_logic;
reset: in std_logic;
output : out std_logic);
end SM;
architecture Behavioral of SM is
signal next_state, current_state: std_logic_vector (2 downto 0);

begin
process(clock, input,current_state)
begin
if (clock'event and clock = '1') then
current_state <= next_state;

elsif reset = '1' then
next_state <= "000";

elsif current_state="000" then
if (input='0') then
next_state<="001"; -- output should be 01
else
next_state<="010";-- output should be 10

end if;

elsif current_state="001" then -- in=0 out 01
output<='0';
next_state<="011";
elsif current_state="011" then
output<='1';
next_state<="000";


elsif current_state="010" then -- in 1 out 10
output<='1';
next_state<="100";
elsif current_state="100" then
output<='0';
next_state<="000";


end if;

end process;
end behavioral ;
 

please anyone can help me with the code
 

now you changed it to an unsynthesisable template. You have to put everything inside the clock branch, or in a completly separate process.

You never answered FvM's question - why have you not used an enumerated state variable like this:

type state_t is (idle, output_1, output_0);

And have you followed his advice to sketch the waveform before writing the code? You could even try drawing the schematic too.
 

i am using xiling, we never used idle before . what i need to do is to put 01 for input of 0 and output 10 for input of 1. maybe i can do the output in half of the clock cycle so i get 2 output in 1 cycle
 

From the sounds of your posts, I really suggest you try and draw the circuit diagram of what your are trying to do BEFORE re-writing your code. VHDL is a DESCRIPTION language, because you decribe a circuit.
 

Here is an example implementation based on an Altera Quartus FSM template

Code:
-- modified Quartus II VHDL Template
-- Four-State Moore State Machine

-- A Moore machine's outputs are dependent only on the current state.

library ieee;
use ieee.std_logic_1164.all;

entity four_state_moore_state_machine is

   port(
      clk    : in std_logic;
      input  : in std_logic;
      reset  : in std_logic;
      output : out std_logic
   );

end entity;

architecture rtl of four_state_moore_state_machine is

   -- Build an enumerated type for the state machine
   type state_type is (s0, s1, s2, s3);

   -- Register to hold the current state
   signal state   : state_type;

begin

   -- Logic to advance to the next state
   process (clk, reset)
   begin
      if reset = '1' then
         state <= s0;
      elsif (rising_edge(clk)) then
         case state is
            when s0 =>
               state <= s2;
            when s1=>
               state <= s3;
            when s2 | s3 =>
               if input = '1' then
                  state <= s0;
               else
                  state <= s1;
               end if;
         end case;
      end if;
   end process;

   -- Output depends solely on the current state
   process (state)
   begin
      case state is
         when s0 =>
            output <= '1';
         when s1 =>
            output <= '0';
         when s2 =>
            output <= '0';
         when s3 =>
            output <= '1';
      end case;
   end process;
end rtl;
 

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