dragonfury
Member level 4
I am facing a netlist error while running a test bench circuit which has only a single OTA subcircuit .
It was working okay after i completed the test bench and ran some simulations on it.
After that I wanted to simulate the post layout of that OTA circuit, for which i simply inserted the extracted file name as performed in the last part of this tutorial (Cadence Tutorial 6). After running once and giving fine result, now when i remove the extracted part and run only the schematic it gives netlist errors.
Please can anyone help me in this issue. I have tried to delete the netlists and also saving a new OTA by copy pasting from the previous , with zero DRC , extraction or LVS errors.but still the issue is there.
Regards
It was working okay after i completed the test bench and ran some simulations on it.
After that I wanted to simulate the post layout of that OTA circuit, for which i simply inserted the extracted file name as performed in the last part of this tutorial (Cadence Tutorial 6). After running once and giving fine result, now when i remove the extracted part and run only the schematic it gives netlist errors.
Please can anyone help me in this issue. I have tried to delete the netlists and also saving a new OTA by copy pasting from the previous , with zero DRC , extraction or LVS errors.but still the issue is there.
Regards
