Mutli-Output Gates and Combinational Arcs in Sequential Cells: RTL Compiler

Halo,

I'm having some trouble with synthesizing a design using a T flip flop with multiple outputs. The T flip flop has both a sequential and a combinational output, where the combinational output acts as an enable for subsequent T flip flops when they are used in a counter design. RTL Compiler gives the following warnings and fails to use the cell for synthesis:

Warning : Detected a combinational timing arc in a sequential cell. [LBR-75]
: The library cell will be treated as a timing-model. Make sure that the timing arcs and output function were described correctly. If the cell was intended to have dual-functionality this may be ok, but this cell cannot be unmapped or automatically inferred.

I need this cell to work as it will optimize area efficiency for the design. If I remove the combinational arc from the T flip flop, RTL Compiler adds the functionality of the combinational arc to the design in the form of individual cells. Why cant it use the functionality when it is integrated into a single standard cell?

Thanks

That's a kind of question that can be answered only by people who actually coded RTL compiler. If the tool was designed accordingly, I don't see why it cannot use it for mapping, but I bet it depends on how the tool is designed.

Is there any way to get past this and to make the tool use the cell?