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Voltage rating of Series capacitor in primary of full-bridge smps

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grizedale

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What voltage rating should be the capacitor in series with the primary of a full-bridge smps.?

The Vin is 330VDC (its offline from 230VAC)

I need this capacitor to not blow up in case of output short circuit or persistent overload.
 

For Vin = 330VDC , giving slight tolerence 400V-DC is minimum requirement. Capacitor in series or parallel(filter capacitor)?
 
Hi,

thanks, i am speaking of the capacitor in series with the full bridge primary.

It is 820n.

I have a primary current limit set at 10Amps.........the maximum possible on time is 9us.

with 10 Amps flowing in the 820n for 9us, this would give rise to a dv of 120Volts....so i cannot really see how this capacitors terminal voltage can go above 120V?
 

A fail safe design would assume full bus voltage across the capacitor, I think.
 
The thing is, i have a primary current sense transformer, to help limit primary current, and at the output there are output inductors.....so the primary current is limited.

i cannot see the primary current being high enough for long enough to charge this series capacitor to above Vin/2 at the most.

It is crucial to get this capacitor as small as possible, since it makes the primary switching loop far easier to lay out.

-also, these low dissipation film capacitors are expensive.
 

When my voltage mode full-bridge gets overloaded, it will stop being voltage mode and go into cycle by cycle current limiting mode...........in this cycle-by-cycle mode, will the capacitor in series with the primary end up getting charged up to the rail voltage?


...and as such, will i need to rate this capacitor to 400V, for this reason?
 

how do i know if its symetrical or asymetrical?

surely it would be extremely unlikely to be "exactly" symetrical?

Our SMPS may be in overload for considerable periods, and we wish to know if the cap in series with the primary needs a 400V rating....so that if charged up to the rail voltage, it wont blow up.
 

If used full wave rectification and maintaining switching duty cycle equel for two half cycles of full wave, even this capacitor can be avoided. in full bridge tropology this is not a big problem. See motor speed controllers using full bridge. Motor is controlled, stopped at ov (no dc offset}.
 
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It depends. A motor inverter will usually implement a phase current measurement and can easily achieve zero DC current by a compensating control loop if necessary. Without current measurement, you have to rely on perfect switching time symmetry. I expect, that it will work in most cases without additional means.
 
hi,,

in a full bridge thats gone into cycle by cycle current limiting, "perfect symetry" is surely not possible....and so the capacitor in series with the prrimary will get charged up to the rail voltage.?
 

My symmetry considerations are referring to ALERTLINKS comment, that you won't need a capacitor. I'm also under the impression, that most full bridge converters are avoiding it. Without a capacitor, current limiting tends to balance the DC across the primary winding and won't cause additional problems. But you have to care for sufficient symmetry in normal operation.

If you have a capacitor, then it should be rated for the bus voltage, as I previously mentioned.
 
If you have to use low voltage rattings, reduse attack and decay time (response) of automatic pwm adjustment. There is no offset voltages in normal operation, it developes only during adjusting. In a similar case, i had used 1/3 voltage rating to bus. which was available. Still in use for many months without a problem.
 
Hi,
I also want to simulate 3K fullbridge DC DC converter with the following parameters in LT spice with 95% efficiency. Here the problem is how to find the transformer specifications like leakage inductance and inductance. In my simulation Iam getting 92% efficiency but the Pi = 956w and Pout = 877w where as Iam aiming for 3k output power. Which parameters i can change to get my target power. can any one provide me the formulas to find these parameters? if you provide me the spice model for this i would be thank full.
Here Iam doing sodt switching in the primary side and synchronous rectification at the secondary side.

https://obrazki.elektroda.pl/1334109400_1377026317.jpg

my specifications are:
i/p vol - 400v
o/p voltage - 28v
o/p power - 3kw
Frequency - 1mhz
 

You have already posted the specification in another thread 4 months ago. Does this mean there's no essential progress in your project since then?
https://www.edaboard.com/threads/285284/

Regarding designing transformer leakage inductance at will, I basically agree to the answer mtwieg has given before.

It sounds rather unlikely that 3 kW can be achieved with a single quad of SPA11N80C3. As another point, transformer core and skin/proximity effect losses will be huge at 1 MHz. They are most likely not realistically modelled in your simulation, so efficiency numbers might need correction.
 

This thread looks familiar...

Have you actually quantized where the sources of the power loss are in your simulation? Knowing that would help a lot, and it should be simple to do.
 

Thank you for reply,

I have put a 13ohm resistance at the Mosfet gate drive now Iam getting 3141watts at the input side and 1752watts at the output side with 55.7% efficiency Iam observing most of the loss is in the Transformer part because the current at Lp is 6Amps and current at Ls is 60Amps it is multiplying only 10times but it should multiply 14 times to get 107Amps on the secondary side.
Here i have taken Lp=0.2261m Ls=1.1536u to satisify 14:1turns ratio is this correct? what strategy i should follow to select primary and secondary inductance?
in the primary side it is softswitching, i have taken dutycyle = 45%
 

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