ADC Need To Understand Some Features

Hello;

I'm new be in Analog Design, Can You please me Give me more details to understand some ADC features:

ADC conversion rate 1 MHz
12-bit resolution
Up to 26 multiplexed channels

Big Thanks

Sample frequency or conversion rate is the speed at which the converter outputs a new binary number.

Sampling rate - it is the rate at which the ADC took analog samples .
Technically it is the rate in which the sample and hold circuit takes data

Conversion rate - it is the rate at which digital signals, ADC outputs, are produce on a continous mode conversion.
It will take a lot of clock cycles to do that. so Conversion rate is Clock rate / needed clock cycles .

The resolution of the converter indicates the number of discrete values it can produce over the range of analog values. The values are usually stored electronically in binary form, so the resolution is usually expressed in bits. In consequence, the number of discrete values available, or "levels", is a power of two. For example, an ADC with a resolution of 8 bits can encode an analog input to one in 256 different levels, since 2^8 = 256. The values can represent the ranges from 0 to 255 (i.e. unsigned integer) or from −128 to 127 (i.e. signed integer), depending on the application. (2^12 = 4096 different levels)

Multiplexing

Sampled-Data Systems
An ideal data acquisition system uses a single ADC for
each measurement channel. In this way, all data are
captured in parallel and events in each channel can be
compared in real time. But using a multiplexer, Figure
3.01, that switches among the inputs of multiple channels
and drives a single ADC can substantially reduce
the cost of a system. This approach is used in so-called
sampled-data systems. The higher the sample rate, the
closer the system mimics the ideal data acquisition
system. But only a few specialized data acquisition
systems require sample rates of extraordinary speed.
Most applications can cope with the more modest
sample rates typically offered by mainstream data
acquisition systems.

Sample and Hold ADCs
Time Skew
A multiplexed ADC measurement introduces a time skew among
channels, because each channel is sampled at a different time.
Some applications can’t tolerate this effect. But a sample and hold
circuit placed on each input ahead of the multiplexer remedies
time-skew problems. In a simultaneous sample and hold circuit
(SS&H) each channel is equipped with a buffer that samples the
signal at the beginning of the scan sequence. The buffer output
holds the sampled value while the multiplexer switches through
all channels, and the ADC digitizes the frozen signals. In a good
simultaneous sample and hold implementation, all channels are
sampled within 100 ns of each other.

Read pages 1..3
https://www.mccdaq.com/PDFs/specs/Multiplexing-and-Sampling.pdf