yhoazk
Newbie level 1
Hi,
I'm having problems simulating a project with mixed HDL (vhdl & verilog) I have RTL source code in both VHDL and Verilog, I get the *.ncd file from ISE implementing the design; then I get the *.sdf file and the net list running netgen tool, also I get the compiled libraries running compxlib tool.
Until this point there is no problem, but my VHDL test bench is calling a packet which is now included in the netlist generated with netgen tool. My first thought was to compile the hdl using vlogan & vhdlan tools
But (I'm not sure about this->) the *.sdf file it was created for the net list not for the top entity of my design.
So how do I include the test bench? Or the correct work flow to simulate this project.
Thanks.
TB: VHDL
RTL: VHDL & Verilog
FPGA: virtex
VCS: VCSMX E-2011.03
ISE: 10.1
I'm having problems simulating a project with mixed HDL (vhdl & verilog) I have RTL source code in both VHDL and Verilog, I get the *.ncd file from ISE implementing the design; then I get the *.sdf file and the net list running netgen tool, also I get the compiled libraries running compxlib tool.
Until this point there is no problem, but my VHDL test bench is calling a packet which is now included in the netlist generated with netgen tool. My first thought was to compile the hdl using vlogan & vhdlan tools
But (I'm not sure about this->) the *.sdf file it was created for the net list not for the top entity of my design.
So how do I include the test bench? Or the correct work flow to simulate this project.
Thanks.
TB: VHDL
RTL: VHDL & Verilog
FPGA: virtex
VCS: VCSMX E-2011.03
ISE: 10.1
