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Synthesis flow in leonardo then to modelsim

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gezzas525

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Hi, iam using UMC 0.18u standard cell library in leonardo spectrum via fpga advantage. Iam not clear on the process of the flow. After synthesising a design I want to then obtain a real model to simulate in modelsim i.e. with delays etc.. some how using the .sdf format. Ive tryed various things but I cant seem to obtain the timing information, everything remains "ideal".

KLEO
 

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