rockybc
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Hi, guys, I need ur help,thx!
I have problems while elaborating the FFT_256 project from opencores.org(Pipelined FFT/IFFT 256 points processor :: Overview :: OpenCores) in the synopsys design compiler. I dont know why this happen because I synthesized the same design in Virtex4 FPGA using synplify 2009 and ISE 9.1 without any problem. Can anyone please point me out what cause the error below?
Here's error information:
Error: Width mismatch on port 'DOR' of reference to 'MPUC1307' in 'FFT16_nb10'. (LINK-3)
Error: Unable to match ports of cell U_FFT1/UM1307 ('MPUC1307') to 'MPUC1307_nb13'. (LINK-25)
Error: Width mismatch on port 'DOR' of reference to 'MPUC1307' in 'FFT16_nb12'. (LINK-3)
Error: Unable to match ports of cell U_FFT2/UM1307 ('MPUC1307') to 'MPUC1307_nb15'. (LINK-25)
I wanna see the equivalent gate count for the project FFT_256 ,so I set the target_library to gtech.db,to build a gtech netlist. Here's the dc script i used,and the top's FFT256
####set library#############
set target_library gtech.db
set link_library "* gtech.db"
set symbol_library class.sdb
##analyze + elaborate
define_design_lib work -path ./WORK
analyze -f verilog ./fft256/bufram256c.v
analyze -f verilog ./fft256/cnorm.v
analyze -f verilog ./fft256/mpuc541.v
analyze -f verilog ./fft256/mpuc707.v
analyze -f verilog ./fft256/mpuc924_383.v
analyze -f verilog ./fft256/mpuc1307.v
analyze -f verilog ./fft256/ram256.v
analyze -f verilog ./fft256/ram2x256.v
analyze -f verilog ./fft256/rotator256_v.v
analyze -f verilog ./fft256/wrom256.v
analyze -f verilog ./fft256/fft16.v
analyze -f verilog ./fft256/fft256.v
elaborate FFT256
#current_design = FFT256
###report all warnings and errors
#check_design
##uniquify because of the mig boundary cells
#uniquify
#link
#compile
when I elaborate FFT256,the error message appear above.Why this happened,for lack of link library or the RTL code?The RTL code could be synthesized in synplify and ISE 9 without any problem.So plz. help, waiting for your answer.
I have problems while elaborating the FFT_256 project from opencores.org(Pipelined FFT/IFFT 256 points processor :: Overview :: OpenCores) in the synopsys design compiler. I dont know why this happen because I synthesized the same design in Virtex4 FPGA using synplify 2009 and ISE 9.1 without any problem. Can anyone please point me out what cause the error below?
Here's error information:
Error: Width mismatch on port 'DOR' of reference to 'MPUC1307' in 'FFT16_nb10'. (LINK-3)
Error: Unable to match ports of cell U_FFT1/UM1307 ('MPUC1307') to 'MPUC1307_nb13'. (LINK-25)
Error: Width mismatch on port 'DOR' of reference to 'MPUC1307' in 'FFT16_nb12'. (LINK-3)
Error: Unable to match ports of cell U_FFT2/UM1307 ('MPUC1307') to 'MPUC1307_nb15'. (LINK-25)
I wanna see the equivalent gate count for the project FFT_256 ,so I set the target_library to gtech.db,to build a gtech netlist. Here's the dc script i used,and the top's FFT256
####set library#############
set target_library gtech.db
set link_library "* gtech.db"
set symbol_library class.sdb
##analyze + elaborate
define_design_lib work -path ./WORK
analyze -f verilog ./fft256/bufram256c.v
analyze -f verilog ./fft256/cnorm.v
analyze -f verilog ./fft256/mpuc541.v
analyze -f verilog ./fft256/mpuc707.v
analyze -f verilog ./fft256/mpuc924_383.v
analyze -f verilog ./fft256/mpuc1307.v
analyze -f verilog ./fft256/ram256.v
analyze -f verilog ./fft256/ram2x256.v
analyze -f verilog ./fft256/rotator256_v.v
analyze -f verilog ./fft256/wrom256.v
analyze -f verilog ./fft256/fft16.v
analyze -f verilog ./fft256/fft256.v
elaborate FFT256
#current_design = FFT256
###report all warnings and errors
#check_design
##uniquify because of the mig boundary cells
#uniquify
#link
#compile
when I elaborate FFT256,the error message appear above.Why this happened,for lack of link library or the RTL code?The RTL code could be synthesized in synplify and ISE 9 without any problem.So plz. help, waiting for your answer.
