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What should be output when you specify conflicting constraints?

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huckle

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Maybe some people may find this interesting...

Lets say designer by mistake specified conflicting sdc constraints on a design? What should be the output?

I'll give one example, false path followed by mulicycle path on the same endpoints?
Can you think of a conflicting constraint for max_delays?

Regards,
-huckle
 

I will take this in priority wise the constarints.
As false path has more priority than multicycle path it would take the path as false path and not do the timing analysis there.

It will report though, so that u know u have made a mistake and u can correct it.

For ur information this is the priority for PT

1. set_false_path
2. set_max_delay and set_min_delay
3. set_multicycle_path


Hope it helped.
 
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    huckle

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When you have such issue it is easy to find by reporting exceptions
 

when conflicting SDC's comes into picture, the more stringent constraint will be used by the synthesizer.
 

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