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net balsting in verilog

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sakshi gupta

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1)Is net name '\a9_apb_prdatasys[0]' in verilog avalid syntax ?

2) will such net names cause some issues in Frontend Flow ?:evil:
 

1) Yes it is valid
2) Generally should not cause any issue in front end. But, it is highly not recommended in normal conditions. You can find this recommendation in Cadence, Mentor Verilog reference manuals.
 

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