Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
your title and your question in the post are 2 different things.
Elexan has anwered your question in the post.
But for the question in the title - std_logic_vector is not a number, so you have to type convert via the unsigned or signed type to get a std_logic_vector. My main question is why do you want to assign a decimal number to a std_logic_vector? a std_logic_vector is just a load of bits. The signed and unsigned types are meant to be treated like integers. ANd on that note, you can do this:
By "decimal number" I (vaguely, I admit) implied an easy alternative to 32 zeros. Alexan_e, thank you for reminding me of others=>'0' ... I should've known this. :-|
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
