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voltage controlled cap

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danda821

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voltage controlled capacitor verilog a

Does anyone know how to add a voltage-controlled cap in Cadence IC? I found a vccap model in analogLIb, but it can be only used in HspiceS. I want to use spectre simulator. Do I need to use Verilog-A or spectreHDL to model the device? Thank you.
 

vccap cadence

With veriloga we can write more flexible models than hspice's vccap. I suggest you use veriloga.
 

spice vccap

u can use Behavioral Cap in Hspice:
Cxxx net1 net2 "C=f(Vctrl)" TYPE=0,1,2

hope it can help u!
 

voltage controlled capacitor

danda821 said:
Does anyone know how to add a voltage-controlled cap in Cadence IC? I found a vccap model in analogLIb, but it can be only used in HspiceS. I want to use spectre simulator. Do I need to use Verilog-A or spectreHDL to model the device? Thank you.
Click to expand...

You can just use a PMOS FET, hook the S and D to GND, and gate to the node desired. The substrate is your control handle. Apply a voltage to it. I know it works that way through two chips fabricated via MOSIS.
 

voltage controlled capacitor in veriloga

danda821 said:
Does anyone know how to add a voltage-controlled cap in Cadence IC? I found a vccap model in analogLIb, but it can be only used in HspiceS. I want to use spectre simulator. Do I need to use Verilog-A or spectreHDL to model the device? Thank you.
Click to expand...

did you solved this problem? if you have the modified model, can you share it with me?
 

cadence voltage controlled capacitor

In the CDF model parameter form, you can enter a form for your cap with all the voltage coefficients. You refer to CDF parameter manual in Cadence
 

cadence vccap

Vamsi Mocherla said:
In the CDF model parameter form, you can enter a form for your cap with all the voltage coefficients. You refer to CDF parameter manual in Cadence
Click to expand...

actually the voltage controlled capacitor we are looking for is not a simple varactor.

the control voltage should be independant on the voltage applied to the capacitor. so it is a four terminal device.
 

cadence voltage controlled capacitance

Then you can model a behavioural model using Verilog A with the cap value controlled by some other voltage
 

spectre model voltage controlled capacitor

try this:

Code: 
`include(disciplines)

module vari_cap( c_p, c_n, Vctrl_p, Vctrl_n);
  electrical c_p, c_n, Vctrl_p, Vctrl_n;

  parameter C, Co=1.0;

  analog begin
     C<+  Co*V(Vctrl_p,Vctrl_n);
     I(c_p,c_n)<+ C*ddt(V(c_p,c_n));
  end
endmodule

And kindly tell me if it worked or even if it has some bugs (I just wrote it, but didn't run!!!)

Regards,
Ahmad,
 

voltage controlled cap model

Hi,
I tried to simulate it but there were some errors in the code, I tried to correct it but it didn't work.
I'm a beginner in Verilog A, could you please tell me how it works?
Thanks
[/quote]
 

In case anyone needs it. I designed a voltage controlled cap where the capacitance is linearly dependent on Vp-Vn.

Code: 
`include "constants.vams"
`include "disciplines.vams"

module vccap(Cp, Cn, Vp, Vn);

	input Vp, Vn;
	inout Cp, Cn;

	electrical Cp, Cn, Vp, Vn;

	real C;

	parameter real C0 = 0;
	parameter real CS = 1;

	analog begin	
		C = CS * V(Vp,Vn);
		I(Cp,Cn) <+ C * ddt(V(Cp,Cn)); 
	end

endmodule
 

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