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[SOLVED] Artisan memory compiler problem

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soloktanjung

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Hello,

I generate a dual port sram using Artisan, then converted to .db file, set search_path and link_library pointed to the sram, and instantiated in my verilog code. I am using synopsys design compiler.

But I got large timing violation problems on the CLKA and CLKB port of the memory. When I looked using "timing analyzer" as shown in the picture attached, there is a weird component that cause the large delay.

Can anyone please tell me what is the component, and what is the problem?

Thanks in advance.

Best,
Hairo
 

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    sram.jpg
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from the picture, what I can tell is:
it is a hierarchy pin and it is the clock.
It may be the latency of the clock tree if your timing analyzer can estimate the latency of clock tree at this stage.

In synthesis, you can set the clock as ideal; therefore, the clock tree will have zero latency.
In place and routing, CTS will do clock tree optimization, which then handle the clock latency problem.
 
Hello WSONG,

Thank you for your explanation. It is solved!

Best,
Hairo
 

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