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[SOLVED] Amba axi bus design steps

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HonoraS

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Hello everybody,
i am new in Hardware design have a project in designing an AXI Bus in VHDL and testbench in SystemC (Co-verification). I read some documentation and have understood how it works, now could some experienced persons tell me which are the steps i should follow, for example what are the different VHDL entities i will need (Channels, Decoder, Arbiter...)
my next question is the following:
must i design the bridge to the low speed slaves myself? and what about the APB?
If you have sample code (verilog is also welcome), please share with me.
Thanks
 

Start with a list of functionality that you intend to support. Not everything in the spec is required. If you want to include APB and AHB with AXI interconnect, then yes, you would need some sort of bridging function. You also need to look at what architecture you intend to support (i.e. section 1.2.2 Interface and Interconnect). If you are new to design, you may want to start with something simple like AHB. There is an AXI implementation on Opencores.org, but it is not in VHDL or verilog.
 
ljxpjpjljx said:
you have VHDL library? why you don't use Verilog to design?
Click to expand...

Hello, thank u for the response, I cannot use Verilog because i am not allowed to do so. The university only allows VHDL and SystemC

---------- Post added at 13:35 ---------- Previous post was at 13:27 ----------

Thanks for the response, I also think that AHB is a little bit simpler, but the prof wants us to start with AXI. Does someone has sample code for axi in vhdl?
THX
 

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