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PLL---> VCO control voltage

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Ayyanar M

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PLL---> Problem on locking @ 500MHz

Hi,


See the attachment and give me a solution.

Issue:(related to each one)

1) There is no variation in the VCO control voltage after the settling time reached(Equal charging and discharging occurs)

2) Up error only maintaining after the settling time(There is no down error)

3) Frequency is oscillating @ 470MHz<500MHz<530MHz(see the attachment)


problem is more but solution is only one(I think so)


 
Last edited:

Ayyanar M , hi!

its look like your loop is unstable.
PFD frequency is 20MHz? C-R-C filter is used? If yes, which value of R?
Really VCO gain is 1.7GHz/V ?? Its so much.

Best reguards Alex
 

thanks AlexVD.

i am having phase margin more than 60deg then how my system is unstable?

R=12Kohm ,C1=130pF,C2=3pF( C-R-C filter)


am genaerating 40MHz-500MHz thats why VCO gain is 1.78GHz/V...(this is small only)
 

Ayyanar M ,

I have simulated your loop with next parameters:
PFD freq=20MHz C1=130pF (standing alone), C2=3pF, R=12k, VCO gain is 1.78GHz/V, I=20uA, Fvco=500MHz

The phase margin of your loop is about 1-2 degree!!!
Recalculate your loop filter.

Best reguards,
Alex
 

Hi AlexVD,


Me too simulated for the same para,meters and also i attached the snapshot ....


i got 71deg phase margin...... (If u have TB pls forward ) (Am using CADENCE tool)

 

Ayyanar M ,
Try to check your cadence results whith a program for calculating the loop parameters (ADSimpll from Analog devices), or EasyPLL Loop Filter Design Tool from national semiconductor.

AlexVD

---------- Post added at 13:04 ---------- Previous post was at 12:28 ----------

Ayyanar M , you can use simpll program from **broken link removed**

Best reguards,
AlexVD
 

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