what is the differnce between adpll and pll

what is the differnce between adpll and pll

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functions of PLL

a dpll is a digital version. Therefore it take a digital input and may consist of a serial shift register which takes this input with a local clock and a phase correction circuit adjusts the local clock to be in phase with the received signal e.g.ethernet.

A dpll is a the digital subset of PLL's in general. A PLL can also be in the analog domain with a feedback control loop.

check these discussion
https://www.edaboard.com/threads/53448/
All Digital Phase-Locked Loop (ADPLL)
http://www.ssc.pe.titech.ac.jp/publications/2006/20060724_win.pdf
Phase-locked loop - Wikipedia, the free encyclopedia

: what is the differnce between adpll and pll

PLL :
A phase-locked loop or phase lock loop (PLL) is a control system that tries to generate an output signal whose phase is related to the phase of the input "reference" signal. It is an electronic circuit consisting of a variable frequency oscillator and a phase detector. This circuit compares the phase of the input signal with the phase of the signal derived from its output oscillator and adjusts the frequency of its oscillator to keep the phases matched. The signal from the phase detector is used to control the oscillator in a feedback loop.
Frequency is the derivative of phase. Keeping the input and output phase in lock step implies keeping the input and output frequencies in lock step. Consequently, a phase-locked loop can track an input frequency, or it can generate a frequency that is a multiple of the input frequency. The former property is used for demodulation, and the latter property is used for indirect frequency synthesis.
Phase-locked loops are widely used in radio, telecommunications, computers and other electronic applications. They may generate stable frequencies, recover a signal from a noisy communication channel, or distribute clock timing pulses in digital logic designs such as microprocessors. Since a single integrated circuit can provide a complete phase-locked-loop building block, the technique is widely used in modern electronic devices, with output frequencies from a fraction of a hertz up to many gigahertz.

Variations
There are several variations of PLLs. Some terms that are used are analog phase-locked loop (APLL) also referred to as a linear phase-locked loop (LPLL), digital phase-locked loop (DPLL), all digital phase-locked loop (ADPLL), and software phase-locked loop (SPLL).[8]
Analog or Linear PLL (LPLL)
Phase detector is an analog multiplier. Loop filter is active or passive. Uses a Voltage-controlled oscillator (VCO).
Digital PLL (DPLL)
An analog PLL with a digital phase detector (such as XOR, edge-trigger JK, phase frequency detector). May have digital divider in the loop.
All digital PLL (ADPLL)
Phase detector, filter and oscillator are digital. Uses a numerically-controlled oscillator (NCO).
Software PLL (S
Functional blocks are implemented by software rather than specialized hardware.


ADPLL:
The phase-locked loop (PLL) is used many applications from cellular base stations to industrial systems and processes. A PLL is a feedback system that, under certain given conditiPLL)ons, dynamically reduces phase and/or frequency offset between a received signal and a locally generated carrier to zero. This is of crucial importance in communications systems receivers that suffer degradation in demodulated signal to noise ratio (SNR) due to phase error. The All-digital phase locked loop (ADPLL) is a phase lock loop implemented in purely digital circuitry and operating on finite precision digital words.

The phase detector deduces the difference in phase between its two input signals. Phase detectors can be implemented in numerous ways, including an XOR gate implementation, a J/K flipflop phase detector, a digital multiplier, Nyquist-rate phase detector (NRPD), or a Hilbert transform phase detector. This reference design uses a digital multiplier that outputs a DC term proportional to the phase difference and series of higher frequency components. The high-frequency terms arising from multiplication in the phase detector are filtered out by the loop filter. The loop filter is usually a first or second order infinite impulse response (IIR) low-pass filter. The filter output is passed to the numerically controlled oscillator (NCO), adjusts phase and frequency to reduce phase error to zero, a condition known as phase lock.

For the locked condition to be attainable, the frequency of the reference signal must be within a defined distance from the free-running or open loop frequency of the NCO, known as the pull-in range. Another important parameter is the hold range, which defines how large the frequency deviation can be between the two signals before they unlock. The amount of time required for the loop to become locked is known as the pull-in time. These parameters can be strictly controlled by modifying the loop bandwidth of the ADPLL.