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    How to write my own Verilog testbench in Xilinx ISE and simulate it like ModelSim.

    Dear All,

    I am newbie and lastly I was simulating my own testbenches on Modelsim Simulator.Now I do not know the idea
    how to simulate my Verilog HDL testbench codes (not VHDL) in Xilinx ISE.I had already generated my waveform using test bench waveform
    editor in xilinx but i am interested in writing and simulating my own hdl code and then checking the functionality of my design based
    upon my desired inputs.Any one can guide me through steps or reference to some good material.

    ---------- Post added at 20:43 ---------- Previous post was at 19:22 ----------

    I also knew how 2 create test bench using New Source > verilog text fixture but I am confused and want to know how to do it using ISim,especially if i am to use a core from core generator, is there any special steps I had to look for in that case.Thanks a lot.

    •   Alt16th August 2011, 20:43

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    Re: How to write my own Verilog testbench in Xilinx ISE and simulate it like ModelSim

    Have you checkout the group:

    Verilog HDL

    I have posted several verilog testbench examples in the group and will post additional examples in the future.

    Also keep an eye on the book reviews in the group, I'll being posting several more reviews shortly.

    The follow two books cover testbenches quite well:

    Verilog HDL (2nd Edition) by Samir Palnitkar

    FPGA Prototyping By Verilog Examples: Xilinx Spartan-3 Version by Pong P. Chu

    BigDog



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    Re: How to write my own Verilog testbench in Xilinx ISE and simulate it like ModelSim

    Yes you are right and thanks for your time.I knew how to write or simulate a testbench in ISE.The problem is I had instantiated a Block Ram Core in my design and i had wrote testbench for it but its not giving any option to simulate it.After selecting behavioral Simulation from ISE it does not show options(which in all my previous designs are there) like Generate Expected Simulation Results as well as Simulate Behavioral model.
    The only option here is simulate your design using Modelsim simulator.When I select it,it gives an error thats obvious because BRAM Core Definition is not available in Model sim Library.
    My point is how I can simulate such a design having built in cores using ISE.I will appreciate it if you can help on this case.
    regards



    •   Alt18th August 2011, 14:10

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    Re: How to write my own Verilog testbench in Xilinx ISE and simulate it like ModelSim

    What version of ISE are you using? If it's a recent version then it will include ISim as simulator from xilinx, which it will use by default.



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    Re: How to write my own Verilog testbench in Xilinx ISE and simulate it like ModelSim

    http://www.digilentinc.com/Data/Docu...20Tutorial.pdf

    The same concept applies to verilog codes too.
    If we admit that human life can be ruled by reason, then all possibility of life is destroyed.



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    Re: How to write my own Verilog testbench in Xilinx ISE and simulate it like ModelSim

    Hi Vickyuet,

    Here are some possible solutions to your problem. The solution appears to largely depend on the version of ModelSim, ModelSim XE (Xilinx Edition), ISE Simulator.

    What version of ISE are you trying to use?

    In order to simulate the Xilinx BRAMs in Modelsim, ModelSim must be made aware of the Xilinx CoreGen simulation models.
    Here are a few links outline the steps required to prepare the Xilinx CoreGen simulation models for simulation tools like ModelSim:

    Xilinx BRAM Usage Instructions

    ModelSim (SE, PE) - How do I compile the XilinxCoreLib (CORE Generator) libraries?

    Block RAM simulation using ModelSim

    EDK Simgen(Simulation --> Generate Simulation HDL files) will convert your elf files to simulation/behavior/system_init.vhd.

    system.do compiles this file and initialize the BRAM contents.

    So when you changed your C/C++ software, you need to regenerate this file.
    ....
    Design and simulation of BRAM using Xilinx Core generator

    Let me know which version of ISE you are using, this will help me select the correct method.

    BigDog



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    Re: How to write my own Verilog testbench in Xilinx ISE and simulate it like ModelSim

    its Xilinx ISE 8.2i but simulation works fine for other modules having no built in cores in them,issue is in core simulation.one further question can i directly write testbench for core without instantiation in my design just to check the timing of generated core.

    ---------- Post added at 09:10 ---------- Previous post was at 09:01 ----------

    @ vipinlal:

    Thanks but i had read this tutorial before posting the problem is instead of timing waveform icon in figure on page 4 of 10 there appears modelsim icon with text Simulate Behavioral Model and it leads me to modelsim simulation This is the problem.Me using Ise 8.2i



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