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what if set_input_delay is greater than clock period? does it affect the frequency?

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jagadeesh_006

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Hi,

what if the set_input_delay is greater than clock period?
how this will affect max frequency of operation?
how to fix it?

Regards,
jagadeesh
 

hi，jagadeesh_006 ！

I am wandering why u have to do so?

How can DC pick up a STD cell for the "input path" whose delay time is less than 0, since (period - input_delay) is a negtive value.
 
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You need to reduce the working frequency of your design
 


In which situation/condition, we mention set_input_delay more than clock period?
Is this condition possible?
If yes, can any one explain this with example?
 

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