pew007
Newbie level 1
Hey, I'm new to Quartus and I need to draw a schematic for the following Verilog code for an adder:
module adder#(parameter W = 8)
(
input clk,
input [W-1:0] a_i, b_i,
output [W:0] sum_o,
output is_odd_o
);
reg [W-1:0] a_r, b_r;
reg [W:0] sum_r;
reg is_odd_r;
wire [W:0] sum_next;
assign sum_next = a_r + b_r;
assign sum_o = sum_r;
assign is_odd_o= is_odd_r;
always_ff @(posedge clk) //enable SystemVerilog to make always_ff work!
begin
a_r <= a_i;
b_r <= b_i;
sum_r <= sum_next;
is_odd_r <= (sum_o[0]) ? 1'b1: 1'b0;
end
endmodule
can anyone help me please? Thank you!
module adder#(parameter W = 8)
(
input clk,
input [W-1:0] a_i, b_i,
output [W:0] sum_o,
output is_odd_o
);
reg [W-1:0] a_r, b_r;
reg [W:0] sum_r;
reg is_odd_r;
wire [W:0] sum_next;
assign sum_next = a_r + b_r;
assign sum_o = sum_r;
assign is_odd_o= is_odd_r;
always_ff @(posedge clk) //enable SystemVerilog to make always_ff work!
begin
a_r <= a_i;
b_r <= b_i;
sum_r <= sum_next;
is_odd_r <= (sum_o[0]) ? 1'b1: 1'b0;
end
endmodule
can anyone help me please? Thank you!