Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

A Probelm about Power Optimization in Synthesis!

Status
Not open for further replies.
H

horzonbluz

Full Member level 4
Joined
May 1, 2002
Messages
208
Helped
11
Reputation
22
Reaction score
9
Trophy points
1,298
Activity points
1,530
Hi, my dear friends.
I use a multiplier in a circuits, and i found it still works in idle state that can consume huge power. Now i want to reduce its unnecesssary activity to reduce the power consume. Can i use operand isolation method?
And more i use synopsys 2003.06 UNIX version to synthesis my design. Can you have some good idea about reduce the power? :)
 

in the DC serial, there is a powercompiler feature, which will insert clock-gating for groups of register with same enable signals. I don't know if this server your purpose.

regards
 

Hi, gerade, when we synthesis our design, we usually use power compile to insert clock gating. It can reduce the power consume.
So i mean not using clock gating but using oprand isolation method. This method conflict with Clock Gating in usuallly because inserting clock gating is introduced before operand isolation. And more some engineers told me that it could increase area when using the operand isolation method in synthesis. So i doubt that we could use the method in synthesis? I don't want increase area of my design and want reduce power consume.
 

No friends can help me? ???????:(
:( :( :( :( :( :( :( :(
I'm not think it a very difficult problem!!!!
 

Don't let tools do it. You should know when the multiplier should work, so you can pull all input to multiplier to constant on idle state. Operand isolate also use this method to reduce power, but of course tools will not know more about the design than you.
 

hi,
I think clock gating is not suitable for your design, and operand isolation maybe a good solution. and you can do it manually not by tools.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top