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Output resistance(ro) and Channel lenght modulation for short channel devices

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analogartist

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I am trying to understand the effect on channel length modulation (CLM) in short channel devices esp. the effect on output resistance. In Razavi chap 16 , there is an equation for calculation for ro based on which ro increases with Vds due to CLM. I assume velocity saturation is also taken into account in this equation

Can someone throw light on how exactly it happens in simple terms?.. for example CLM causes effective channel length↓, Id ↑ .....terms like that.....
In mos w/o CLM the Ids-Vds curve is flat and slope is zero meaning ro is infinite, with CLM included, slope of Ids/Vds is non-zero and ro becomes finite. meaning CLM effect causes the ro to reduce from infinity to some finite value. then how come when CLM happens in short channel devices, ro is said to increase?.

CLM causes effective channel length↓, Id ↑ but wouldnt that decrease the ro rather than increase ro?. I refered some online notes etc I couldnt find any Ids equations including velocity saturation, CLM, eff Channel lenght and ro.

For simple mosfet modeling Lambda was taken constant and I understand for high level modeling, simulations tools are used to find the Lamba and used in hand calculations as (1+lambda * Vds) for finding Id. I am not trying to do sims at this point ..just trying to understand the phenomenon in simple terms as why ro increases rather than decreases.

on a side note: w.r.t ro, CLM effect takes place when Vgs> Vth. but Drain-induced barrier lowering(DIBL) takes places when Vgs< Vth??...
 

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