[SOLVED] Help in understanding read_sdc command

Can someone please explain to me what a read_sdc command does? thanks in advance.

Reads existing Synopsys Design Constraints Files (.sdc)— with all current constraints and exceptions— that are specified in user-defined order in the Quartus II Settings File (.qsf). If a Synopsys Design Constraints File is not specified in the Quartus II Settings File, the TimeQuest analyzer reads a default Synopsys Design Constraints File named <revision>.sdc. This command also produces the SDC File List report, which lists all Synopsys Design Constraints Files in the current design.

Note: If you access the Read SDC File command from the Constraints menu in the TimeQuest analyzer, you must select an Synopsys Design Constraints File from your local disk.

You access this command by double-clicking Read SDC File in the Tasks pane in the TimeQuest Timing Analyzer.

---------- Post added at 10:52 ---------- Previous post was at 10:39 ----------

This should help you
**broken link removed**

Thank you! I get a better understanding now.
Do you happen to knw what is 'leakage', 'internal' & 'switching' power is for a transistor? in a simple explanation.

Two kinds of power constitute this consumption: active (Pactive ~ CV2f), which is the power used as the device performs its various functions, and leakage (Pleakage ~ IV), which is the power consumed by unintended leakage that does not contribute to the IC's function.

1. Leakage power is primarily the result of unwanted subthreshold current in the transistor channel when the transistor is turned off. This subthreshold-driven leakage power is strongly influenced by variations in the transistor threshold voltage VT (the voltage applied to the gate electrode that turns on the transistor).

hi
karthiga05,


Mr.ckshivaram gave good answer.

Generally the sdc is written in some format based on tcl scripting. It is actually synopsys delay constarints but now everyone uses same.Hence It is named as standard delay constraints.

It is one of the input for synthesizing the rtl design. Without this you can not get your specification for your design.