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if this is an FPGA post, i'd start with the FPGA memory interfaces. MIG, altera's choice. newer FPGAs have hard-IP for memory. If this is for an ASIC, look into other's IP. Or at least look at the standard JEDEC models.
if this is an FPGA post, i'd start with the FPGA memory interfaces. MIG, altera's choice. newer FPGAs have hard-IP for memory. If this is for an ASIC, look into other's IP. Or at least look at the standard JEDEC models.
there are three possible answers.
1.) quit. you are just not capable in this field.
2.) don't quit. attempt to learn from others. explain yourself well and ask good questions that show where any conceptual difficulties might arise.
3.) don't quit but ignore everyone else. try until you get things to work. possibly at great expense to your company or your career.
(ideally, you will chose #2 -- explaining why MIG is confusing to you, what you want MIG to do, etc...)
well if i want send 200 bite per second from ram in to fpga
and my ram is 128
what should i do?
and my ram need refresh each 3.9 micro second
that's my problem in fact
and i hope i explain it good
and by the way this s my first project
I'd start with MIG's example core. Just see if you can get that to work on your FPGA. After that, remove the test code and develop an application. MIG contains state machines that allow it to schedule reads/writes/refreshes etc... It also performs the calibration. You should be concerned with getting the infrastructure set up -- MIG uses multiple clocks. Then with the interface to MIG -- it uses fifos to allow the memory to run in their own clock domain, as well as to allow refresh operation to be performed.
I'm not sure what a ram of 128 refers to. either a bus width, memory size, etc...
If this is your first fpga project ever, and you are new to vhdl as well ... I would suggest that as a first project you try something simpler than anything to do with a ddr2 controller. Or expect a lot of pain^H^H^H^H opportunities to learn new and exciting things!
If this is your first fpga project ever, and you are new to vhdl as well ... I would suggest that as a first project you try something simpler than anything to do with a ddr2 controller. Or expect a lot of pain^H^H^H^H opportunities to learn new and exciting things!
I'd start with MIG's example core. Just see if you can get that to work on your FPGA. After that, remove the test code and develop an application. MIG contains state machines that allow it to schedule reads/writes/refreshes etc... It also performs the calibration. You should be concerned with getting the infrastructure set up -- MIG uses multiple clocks. Then with the interface to MIG -- it uses fifos to allow the memory to run in their own clock domain, as well as to allow refresh operation to be performed.
I'm not sure what a ram of 128 refers to. either a bus width, memory size, etc...
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