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how is the different aspect ration in Block ram?

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hamed_sotoudi

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Hi,
what is the VHDL coding style for different aspect ratio for true dual port block RAM in Xilinx?
 

why do you mean by aspect ratio?

to define a block ram, just do this:
type ram_type is array(0 to N-1) of std_logic_vector(m-1 downto 0);

this creates a ram thats N words by m bits.
 

hamed_sotoudi said:
Hi,
what is the VHDL coding style for different aspect ratio for true dual port block RAM in Xilinx?
Click to expand...

IIRC, at the moment it is "coregen". recently I did a viterbi decoder which used a very wide write and very narrow read. to do this I used the block ram primitive. Had I needed a larger RAM for a longer traceback, a coregen core would have been my choice.

This may change eventually. Xilinx has been behind Altera in terms of tool development. (though altera also has some very severe issues as of 10.1)
 

Hi,
Thanks for your apply
I don't want to use coregen. I want to code dual port ram with one port as 8 bit read/write and other port with 4 bit read/write. is it possible in xilinx or not?(I mean with vhdl code not with coegen)
 

I know you can with Quartus.

First of all you decalare a type thats a pair of std_logic_vectors

type data_word_t is array(0 to 1) of std_logic_vector(3 downto 0);

then create the memory array;

type mem_array_t is array(0 to N-1) of data_word_t;

and then you just access the member differently for side A and side B, with side A writing an entire word, and side B only accessing 4 bits.

That works in Altera.
 
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I don't want to use coregen. I want to code dual port ram with one port as 8 bit read/write and other port with 4 bit read/write. is it possible in xilinx or not?(I mean with vhdl code not with coegen)
Click to expand...
A recent VHDL compiler should be able to "infer" internal or block ram from VHDL code, also for dual port. I'm not aware for the detail rules with Xilinx, but it works well with Altera Quartus. I fear, it won't be supported for different port widths, as you intend. In this case, you have to rely on manufacturer libraries. These are usually parameterizable modules, in so far you can e.g. change the settings without using MegaFunctions (or Coregen). But the parameters and ports will be manufacturer specific in any case. True portable port won't be an option, you have to write wrappers for particular manufacturer libraries.

P.S.:
I know you can with Quartus.
Click to expand...
Also the address mapping will be different for RAMs with different A and B port widths. You have e.g. 16 8-bit words on port A that maps to 32 4-bit cells on port B. I never heard, that it would be supported by the inference mechanism, I even can't imagine the respective HDL syntax right now. But even if it exists, will it be recognized by the compiler?

O.K., you are right. Mixed-Width Dual-Port RAM is shown in the Quartus software handbook!
It has been added in Quartus V10.0. Thank you for mentioning it.

Code VHDL - [expand]
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--Example 6–21. VHDL Mixed-Width RAM with Read Width Smaller than Write Width
library ieee;
use ieee.std_logic_1164.all;
package ram_types is
  type word_t is array (0 to 3) of std_logic_vector(7 downto 0);
  type ram_t is array (0 to 255) of word_t;
end ram_types;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.ram_types.all;
entity mixed_width_ram is
  port (
    we, clk : in std_logic;
    waddr : in integer range 0 to 255;
    wdata : in word_t;
    raddr : in integer range 0 to 1023;
    q : out std_logic_vector(7 downto 0));
end mixed_width_ram;
architecture rtl of mixed_width_ram is
  signal ram : ram_t;
begin -- rtl
  process(clk, we)
    begin
      if(rising_edge(clk)) then
        if(we = '1') then
          ram(waddr) <= wdata;
        end if;
        q <= ram(raddr / 4 )(raddr mod 4);
      end if;
    end process;
end rtl;
 
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