Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

some hvmos structure about bcd process,help

Status
Not open for further replies.

bm429

Newbie level 5
Joined
Mar 10, 2007
Messages
10
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,352
hi everyone

i saw some unknown mos structure recently, it's about bcd process.

i post it in the attachment.

i hope someone can tell me what the hvmoses are? ldmos or vdmos or just some demos? and give me some information about the characteristics when i want to design using the
devices.

of course , the details about the mos are welcome

thanks a lot
 

Attachments

  • POLY_LAYER.bmp
    873.1 KB · Views: 57
  • PIC1.bmp
    457.2 KB · Views: 56

all of them (ldmos, vdmos and demos) can be used as high voltage mos.
Generally, >5V can be regarded as high voltage mos.
 

The honeycomb gate, heavy contacts outside the well and
the "ghost" of a buried layer is a giveaway that "POLY_LAYER"
is a vertical or quasi-vertical device.

The other one looks like a plain longish channel FET to me.
 

thank for you reply.

but i am not familiar with the quasi-vertical device and plain longish channel FET .

can you tell me more details about them?
 

**broken link removed**
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top