How can I input assembly language problem directly into my RAM

Hello everyone, My name is Jo and I came from JPN.

I have designed a 8-bit processor with HDL and all the blocks have been testbench.
My 8-bit processor named hibikino.and there are 7 blocks in it.
U1:tri-stage U2:accumulator U3:register U4:ALU U5:control logci U6 PG counter U7 multiplexer
//..............................................hibikino code........................................//
module hibikino (data,addr,clock,reset,halt,mem_wr,mem_rd);
input [7:0] data;
input clock,reset;
output halt,mem_wr,mem_rd;
output [4:0] addr;
wire [7:0] data,accum,alu_out;
wire [4:0] addr,ir_addr,pc_addr;
wire [2:0] opcode;

ts U1 (.accum(accum),.data(data),.data_en(data_en));
register U2 (.clock(clock),.reset(reset),.control(load_ac),.out(accum),.in(alu_out));
register U3 (.clock(clock),.reset(reset),.in(data),.control(load_ir),.out({opcode,ir_addr}));
alu U4 (.alu_out(alu_out),.zero(zero),.data(data),.accum(accum),.opcode(opcode));

ctltop U5 (.zero(zero),.opcode(opcode),.clock(clock),.reset(reset),.halt(halt),.mem_wr(mem_wr),.mem_rd(mem_rd),
.load_ir(load_ir),.load_pc(load_pc),.inc_pc(inc_pc),.load_ac(load_ac),.data_en(data_en),.fetch(fetch));

counter U6 (.clock(clock),.reset(reset),.load_pc(load_pc),.inc_pc(inc_pc),.pc_addr(pc_addr),.ir_addr(ir_addr));
mux U7 (.ir_addr(ir_addr),.pc_addr(pc_addr),.fetch(fetch),.addr(addr));


endmodule
//..............................................hibikino code........................................//


I have also designed a RAM
//..............................................RAM code..........................................//
module ram(addr,mem_rd,mem_wr,data);
inout [7:0] data;
input [4:0] addr;
input mem_rd,mem_wr;
reg [7:0] mem[0:300];


assign data = (mem_rd)? mem[addr] : 8'bzzzzzzzz;

always @(posedge mem_wr)begin
mem[addr]<=data;
end
endmodule
//..............................................RAM code..........................................//



Now the problem is that I have some assembly language program wants be inputed into the RAM directly,
How can I do it?
//........................RAM's instruction area.................................//
00 JMP 03 //00:address JMPperation 03perand
01
02
03 LDA 1B
04 STO 1C
05 ADD 1A
06 STO 1B
07 LDA 1C
08 STO 1A
09 XOR 1D
0A SKZ
0B JMP 03
0C HALT
//........................RAM's instruction area.................................//

//........................RAM's data area.................................//
1A 1
1B 0
1C 1
1D 144
//........................RAM's data area.................................//

word lenghperation 3 bit,operand 5 bit ,total 8bit word
LDA:101 ADD:010 AND:011 XOR:100 STO:110 JMP:111 SKZ:001 HALT:000
for example the first problem is 11100011
the third problem is 10111010

Here is A good link on initializing the RAM content

1.=h**p://www.xilinx.com/itp/xilinx5/data/docs/lib/lib0350_334.html#wp1001508]RAM16X2S

2.h**p://www-mtl.mit.edu/Courses/6.111/labkit/advanced_ise.shtml


/////////////////////////////
reg [7:0] ram [7:0];
initial begin
ram[7] = 8’h02; ram[6] = 8’h00; ram[5] = 8’h08;
ram[4] = 8’h04; ram[3] = 8’h08;
ram[2] = 8’h02; ram[1] = 8’h08; ram[0] = 8’h0D;
end
////////////////////////////

blooz said:

Here is A good link on initializing the RAM content

1.=h**p://www.xilinx.com/itp/xilinx5/data/docs/lib/lib0350_334.html#wp1001508]RAM16X2S

2.h**p://www-mtl.mit.edu/Courses/6.111/labkit/advanced_ise.shtml


/////////////////////////////
reg [7:0] ram [7:0];
initial begin
ram[7] = 8’h02; ram[6] = 8’h00; ram[5] = 8’h08;
ram[4] = 8’h04; ram[3] = 8’h08;
ram[2] = 8’h02; ram[1] = 8’h08; ram[0] = 8’h0D;
end
////////////////////////////

Click to expand...

Thank you very much!

I will try it