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How to obtain layout from VHDL code?

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mazelk

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Hi....

I just have done VHDL codes for microprocessor modules (ALU, registres, PC, etc). Also, I have done basic gates in layout (nor, nand, exor, not), applying Mentor IC.

How can I obtain the layout of this microprocesor, using Mentor IC???

Thanks in advance....
 

mazelk said:
I just have done VHDL codes for microprocessor modules (ALU, registres, PC, etc). Also, I have done basic gates in layout (nor, nand, exor, not), applying Mentor IC.

How can I obtain the layout of this microprocesor, using Mentor IC???

Hi,mazelk

What are you meaning for "obtain'?In my opinion,either VHDL or Verilog modules is constructed by STANDARD CELLs in LAYOUT.You can get them from IC foundry.:)
 

if you have done your RTL coding. you should do synthesis to got library dependent netlist.
THen you can do P&R , at last do mapping to "obtain"
complete layout.

As Flyankh said, all the library is provided by foundry
 

I mean, if I have the basic gates (like nor, nand, not, xor) as layout cells in Mentor IC, how can I get the complete layout (not floorplaner. I want to get layout drawing with polysilice, diffusions, metals, contacts, etc ). I have all RTL by VHDL codes.

Anyone knows how to?
 

Hi mazelk

Why are you so insist on using your layout?The std cells is not worse than yours:)

flyankh
 

there are many ways to do a layout, and when u r in the industry you take what is already done, but, thas doesn't comes from wind, that is done for people like mazelk, so don't tell him "that is done", help him, and you shall learn how to get better performance in your layout
 

If you only have VHDL,and you eithe build the standard cell by yourself,you could rely on a standard cell from some vendor,then using sysnopsys to synthesis and get the final layout
 

that is interesting to me - i don't do digital. (in fact, i think you are in the wrong forum, but who cares!)

are you saying that synopsis can route a standard cell layout from vhdl?

i used a free program called electric which can channel route standard cells from STRUCTURAL vhdl, but cannot convert behavioral vhdl into structural. for those of you not familiar, structural is similar to a schematic - INA of nand2 connected to OUT of nand1. useful, but not great since you have to spend your whole day doing schematic anyway. i want to write my state machines in behavioral, then compile to a simple set of DFF, nand, nor, inv, etc. then channel route is ok.

anyone use this flow? please give specifics, i would like to see your examples if possible, or hear about how it was done.

thanks!
 

Interesting topic,

I'm currently trying to get a bit of layout from VHDL to use in my mixed signal chip. Do you have any information or tutorial on either Mentor IC station or Silicon Ensemble on how to do this?

Greetings,
Steve
 

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