[SOLVED] What is Gate-level netlist?

Hi. I want to knw what is a gate level netlist and what is it used for. can someone help me? the internet isnt much of a help. thanks!

i still dont understand what a gate-level netlist is. is thr a webpage whr i can go which explains theoretically?

a gate level netlist is basically your fitted design, before its converter to a programming file. It contains all of the logic and delays of the final system. It allows you to use your testbench from the simulation testing to test the final design. Simulation is often extremly slow, hence why people avoid simulating them as much as possible. It is best to try and fix bug at the RTL level before moving onto gate level netlists or the real chip.

what do u mean by fitted design?

Look at these tutorials
**broken link removed**
http://inst.eecs.berkeley.edu/~cs250/fa09/handouts/tut2-toolflow.pdf
http://www.ece.uah.edu/~milenka/cpe527-07F/labs/lab5_StandardCellDesignFlow_vhdl2l_mu0.pdf

When you compile a deisng with ISE, Quartus etc, there are 3 main stages (Im following the Quartus names, as this is the tool I use)

First of all you get analysis and synthesis. This syntax checks your code followed by converting it to synthesis netlist. This extracts muxes, adders, memories, logic etc from your code. You can check this in the RTL viewer. It also maps these higher level components to physical LUTs and rams in the real device you are using.

After this stage, the fitter starts, which is usually the slowest part. It takes the mapped netlist from the synthesisor and places all these LUT and rams to the actual parts in the design. It adds all the routing to connect all the LUTs, rams, DSP slices etc. If you have timing constraints set the fitter may be re-run to try and meet timing constraints.

Finally, the fitted design is passed to the assembler where a programming file is generated.

You can get a gate level netlist from post synthesis or post fitter IIRC. The post fit one will contain all the routing delays, whereas the post synthesis will just have element delays.

See this is the verilog file of a module **broken link removed**

and this is the equivalent gate level netlist

**broken link removed**

YOu can see that gate level netlist has only gates.