Question: control/observe points clocked by internal clock

Question: control/observe points clocked by internal hook up pin

Hi,

I met a problem while I put test points with DesignCompiler.

This chip has 5 bit mode pins.
Each mode corresponds to one operation mode, such as FUNCTION_MODE/SCAN_TMODE/BIST_TMODE/JTAG_MODE/....

The hierarchy is,
- top_design (port: PGPx, ...)
-------- PAD
-------- core
---------------- gpio (pin: o_SCLK)
------------------------ U_scan_sclk
...

For SCAN_TMODE (scan test mode), a port named PGP6[7], one of the GPIO ports, is used as SCAN CLOCK.
For other modes, PGP6[7] is just a GPIO port.

Passing through the PAD, PGP6[7] goes into core/gpio, and there, meets an AND gate.
The AND gate cuts PGP6[7] for all the modes except SCAN_TMODE.

verilog code (module: gpio) :
AND2 U_scan_sclk (.A(i_GP6_in[7]), .B(o_SCAN_TMODE), .Y(o_SCLK) );

i_GP6_in[7] is the PAD's output pin for PGP6[7].

I'd like to use U_scan_sclk/Y as the scan clock's CTS root.
So, I declared like this in DesignComplier script:

create_clock -name clk_scan -period $CLOCK_PERIOD_SCAN -waveform [list 0 [expr $CLOCK_PERIOD_SCAN / 2]] [get_pins -h U_scan_sclk/Y]
...
set_dft_signal -view existing_dft -type ScanClock -port PGP6[7] -hookup_pin [get_pins -h U_scan_sclk/Y] -timing {50 80}


Now, I need to put some observe points clocked by U_scan_sclk/Y for the low test coverage.

The problem is,
if I write like this,

set_test_point_element -type observe \
insert_dft generates a net list which uses PGP6[7] as all observe points' clock.
In this case, I can't use U_scan_sclk/Y as CTS root,
because the observe points' clocks begins from PGP6[7], but other F/F's scan clock is from U_scan_sclk/Y.

If I write like this,
set_test_point_element -type observe \

DC says -clock_signal requires PORTS only.

So, going up one hierarchical level higher,
set_test_point_element -type observe \

And, change the set_dft_signal a little bit,
create_clock -name clk_scan -period $CLOCK_PERIOD_SCAN -waveform [list 0 [expr $CLOCK_PERIOD_SCAN / 2]] [get_ports core/gpio/o_SCLK]

In this case, DC says there is NO SCAN CLOCK on port top_design/core/gpio/o_SCLK.
Here's the message.

Error: clock signal type not specified for the port core/gpio/o_SCLK. (TESTXG-27)


How can I put the test points clocked by internal hook up pin?
It is really serious for me.
Please give me some advices how to solve this problem.

Thank you, in advance.