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Help me fix my booth multiplier program

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booth multiplier

Hi, every one, I have written a booth multiplier, But when I simulate it, I found that some times it can work well, some times it can't. I don't know what's wrong with my design. Please help me. Below is my code.


Code: 
module booth_multiplier(product,ready,word1,word2,start,reset,clk);

parameter              L_word=4;
parameter              L_BRC=2;
parameter              S_idle=0,S_shifting=1,S_adding=2,S_subing=3,S_done=4;
parameter              All_ones=4'b1111;

output[2*L_word-1:0]   product;
output                       ready;

input [L_word-1:0]      word1,word2;
input                         start,clk,reset;

reg[2:0]                     state,next_state;
reg[2*L_word-1:0]       multiplicand;
reg[L_word-1:0]          multiplier;
reg                            m_brc;
reg                            shift,Add,Sub,load_words;
reg                            flush;
reg[2*L_word-1:0]      product;

wire                   m0=multiplier[0];
wire[L_BRC-1:0]  BRC={m0,m_brc};
wire                   ready=((state==S_idle)&&!reset)||(state==S_done);
wire                   empty=((word1==0)||(word2==0));

always@(posedge clk or posedge reset) //Datapath configuration
  begin
  if(reset) begin
    multiplicand<=0;
    multiplier<=0;
    product<=0;
  end
  else if(flush)
    product<=0;
  else if(load_words) begin
    if(word1[L_word-1]==0) multiplicand<=word1;
    else multiplicand<={All_ones,word1[L_word-1:0]};
    multiplier<=word2;
    product<=0;
  end
  else if(shift) begin
    multiplicand<=multiplicand<<1;
   multiplier<=multiplier>>1;
  end
  else if(Add) 
    product<=product+multiplicand;
  else if(Sub)
    product<=product-multiplicand;
  end

always@(posedge clk or posedge reset)
  if(reset)
    m_brc<=0;
  else if(load_words)
    m_brc<=0;
  else
    m_brc<=m0;

always@(posedge clk or posedge reset)//state transition
  if(reset)
    state<=S_idle;
  else
    state<=next_state;

always@(state or start or BRC or multiplier or empty)//state machine
  begin
    load_words=0;
    shift=0;
    Add=0;
    Sub=0;
    flush=0;
    case(state)
       S_idle:     if(!start) next_state=S_idle;
	     else if(start&&!empty) begin
                     load_words=1; next_state=S_shifting;
                     end
                     else if(start&&empty) begin
	     flush=1; next_state=S_done;
                     end
      S_shifting: if(multiplier==1) begin Add=1; next_state=S_done; end
	     else if(BRC==2'b00||BRC==2'b11) begin shift=1;     
                     next_state=S_shifting; end
                     else if(BRC==2'b01) begin Add=1; next_state=S_adding; end
	     else if(BRC==2'b10) begin Sub=1; next_state=S_subing; end
     S_adding:   begin shift=1; next_state=S_shifting; end
     S_subing:   begin shift=1; next_state=S_shifting; end
     S_done:     if(start==0) next_state=S_done;
	     else if(start&&empty) begin
                     flush=1; next_state=S_done;
                     end
                     else if(start&&!empty) begin
	     load_words=1; next_state=S_shifting;
	     end
      default:    next_state=S_idle;
    endcase
  end

endmodule
 

Re: booth multiplier

More info, please!

When the multiplier works well, and when not? examine your inputs sequence in both cases and you could find a solution...
 

booth multiplier

maybe you need a diagram to show your design architecture.
 

Re: booth multiplier

See below VHDL version of Booth Multiplier for reference:

--This file contains all the entity-architectures for a complete
--k-bit x k-bit Booth multiplier.
--the design makes use of the new shift operators available in the VHDL-93 std
--this design passes the Synplify synthesis check
----------------------------------------------------------------------
--top level design unit
ENTITY booth_multiplier IS
GENERIC(k : POSITIVE := 7); --input number word length less one
PORT(multiplicand, multiplier : IN BIT_VECTOR(k DOWNTO 0);
clock : IN BIT; product : INOUT BIT_VECTOR((2*k + 1) DOWNTO 0));
END booth_multiplier;

ARCHITECTURE structural OF booth_multiplier IS

SIGNAL mdreg, adderout, carries, augend, tcbuffout : BIT_VECTOR(k DOWNTO 0);
SIGNAL mrreg : BIT_VECTOR((k + 1) DOWNTO 0);
SIGNAL adder_ovfl : BIT;
SIGNAL comp ,clr_mr ,load_mr ,shift_mr ,clr_md ,load_md ,clr_pp ,load_pp ,shift_pp : BIT;
SIGNAL boostate : NATURAL RANGE 0 TO 2*(k + 1);

BEGIN

PROCESS --main clocked process containing all sequential elements
BEGIN
WAIT UNTIL (clock'EVENT AND clock = '1');

--register to hold multiplicand during multiplication
IF clr_md = '1' THEN
mdreg <= (OTHERS => '0');
ELSIF load_md = '1' THEN
mdreg <= multiplicand;
ELSE
mdreg <= mdreg;
END IF;

--register/shifter to product pair of bits used to control adder
IF clr_mr = '1' THEN
mrreg <= (OTHERS => '0');
ELSIF load_mr = '1' THEN
mrreg((k + 1) DOWNTO 1) <= multiplier;
mrreg(0) <= '0';
ELSIF shift_mr = '1' THEN
mrreg <= mrreg SRL 1;
ELSE
mrreg <= mrreg;
END IF;

--register/shifter accumulates partial product values
IF clr_pp = '1' THEN
product <= (OTHERS => '0');
ELSIF load_pp = '1' THEN
product((2*k + 1) DOWNTO (k + 1)) <= adderout; --add to top half
product(k DOWNTO 0) <= product(k DOWNTO 0); --refresh bootm half
ELSIF shift_pp = '1' THEN
product <= product SRA 1; --shift right with sign extend
ELSE
product <= product;
END IF;

END PROCESS;

--adder adds/subtracts partial product to multiplicand
augend <= product((2*k+1) DOWNTO (k+1));
addgen : FOR i IN adderout'RANGE
GENERATE
lsadder : IF i = 0 GENERATE
adderout(i) <= tcbuffout(i) XOR augend(i) XOR comp;
carries(i) <= (tcbuffout(i) AND augend(i)) OR
(tcbuffout(i) AND comp) OR
(comp AND augend(i));
END GENERATE;
otheradder : IF i /= 0 GENERATE
adderout(i) <= tcbuffout(i) XOR augend(i) XOR carries(i-1);
carries(i) <= (tcbuffout(i) AND augend(i)) OR
(tcbuffout(i) AND carries(i-1)) OR
(carries(i-1) AND augend(i));
END GENERATE;
END GENERATE;
--twos comp overflow bit
adder_ovfl <= carries(k-1) XOR carries(k);

--true/complement buffer to generate two's comp of mdreg
tcbuffout <= NOT mdreg WHEN (comp = '1') ELSE mdreg;

--booth multiplier state counter
PROCESS BEGIN
WAIT UNTIL (clock'EVENT AND clock = '1');
IF boostate < 2*(k + 1) THEN boostate <= boostate + 1;
ELSE boostate <= 0;
END IF;
END PROCESS;

--assign control signal values based on state
PROCESS(boostate)
BEGIN
--assign defaults, all registers refresh
comp <= '0';
clr_mr <= '0';
load_mr <= '0';
shift_mr <= '0';
clr_md <= '0';
load_md <= '0';
clr_pp <= '0';
load_pp <= '0';
shift_pp <= '0';
IF boostate = 0 THEN
load_mr <= '1';
load_md <= '1';
clr_pp <= '1';
ELSIF boostate MOD 2 = 0 THEN --boostate = 2,4,6,8 ....
shift_mr <= '1';
shift_pp <= '1';
ELSE --boostate = 1,3,5,7......
IF mrreg(0) = mrreg(1) THEN
NULL; --refresh pp
ELSE
load_pp <= '1'; --update product
END IF;
comp <= mrreg(1); --subract if mrreg(1 DOWNTO 0) ="10"
END IF;
END PROCESS;

END structural;
 

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