Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to implement the global gated clock in RTL level?

Status
Not open for further replies.

irun2

Member level 2
Joined
Jan 20, 2008
Messages
49
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,701
Hi all,
In low power design I've learned that there're some techniques, and one of them is clock gating. There're global/local clock gating.
I know following codes can infer the local one with some proper power compiler directives.
always @(posedge clk)
...
if(clk_en)
q<=d;
...
But in what coding style should be written if I want the global gated clock way?
 

I don't know what you mean by global gated clock.
Gated clock in rtl mean to generate a gated clock enable instead gated data enable.
 

When you talk about synthesis, no one can answer your question without telling us which synthesis tool you are referring to. All the synthesis tool has different feature, coding style, etc..

If you use DC, I think XG can do the global clock gating.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top