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Need help about the stability of LDO

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I am designing a ldo which can drive 50mA current, use a one stage op and a PMOS as output transistor, use internal 100pF cap as output capactor. When I do ac simulation, I find that the pole on OP's output is 18k, the output pole is 4M, and the phase margin is too small. i think the dominate pole should be the output pole, so how to compensate it? Or is the some papers about it? thanks very much!
 

Pls try miller cap to generate lower dominant pole.
 

you mean add miller cap between op and PMOS? So the dominant pole is the OP's out?
 

Yes. Add miller cap between PMOS gate and drain. It will also push output pole to higher freq.
 

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