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Examples of setup time and hold time

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junchaoguo51888

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setup time and hold time

according to conception,the setup time and hold time is simple,
but it look like confused, who can present some example for me
 

Re: setup time and hold time

The best way to learn setup&hold time is to design a ff by yourself and findout the ff's setup&hold time by simulation. That's how I learned the actual meaning of setup&hold time.

here is a simple lecture note on ff.
 

Re: setup time and hold time

The setup time and the hold time work together to make sure the leading edge is centered on the data pulse.The hold time is the minimum duration of the the data pulse with respect to the leading edge and the setup time the phase of the data pulse with respect to the leading edge.
 

Re: setup time and hold time

Easy to grasp & easy to remember:

Hold Time. The life after the edge:

Do think in a active clock edge; ask yourself: how long should I hold this signal in order the clock catch it?. That is the hold time.

Setup Time. The life before the edge:

Do think again in our friend, the active clock edge, and ask yourself: how long before the active edge clock I have to have my signal stable (not changing) so the clock catches it?. That time is the setup time.


If your design doesn´t meet setup and hold times you will have erratic malfuntions or just it will not work at all.
 

Re: setup time and hold time

Hi

perhaps this might help

h**p://www.hardware-guru.com/Interview/D_FlipFlop.htm

Regards
Taring
 

Re: setup time and hold time

Guys, I have two questions in mind when talking about setup and hold times.
The first is about violations - Suppose we have some setup time, say 7ns and we have 1ns setup violation. Does it mean that data arrives 6 ns before the clock edge or it means that data arrives 1ns after the edge?
And the second concerns hold times - what assures that my design has the required hold time. My opinion is that delays of an output signal of a stage with respect to the clock assure the hold time of the next one, for the next clock edge. Is this correct?
 

Re: setup time and hold time

As all knows, a flipflop is composed of two latches. I think the setup time is dependent on the input-to-output data delay of the first latch and the hold time is dependent on the time taken for the first latch to turn off.
 

Re: setup time and hold time

A flip flop is one latch that has a clock input to enable it. The leading edge is derived from the clock. The hold time is the time period after the leading edge. The setup time is the time period before the leading edge. I agree with Basil.
 

setup time and hold time

The difference is ---> or <---, set up time is ---> , means we can get stable signal after that time. hold time is <--- means if you need make sure the signal is valid, the signal must be hold at leat that time
 

Re: setup time and hold time

Yes, in a dynamic circuit type used, a latch can be used as a flipflop with a short clock pulse duration. I knew this kind of circuit is not used often due to its operational instability.
 

setup time and hold time

u refer to floyd which will give u complete idea about this set up and hold time.
 

Re: setup time and hold time

manchev said:
Guys, I have two questions in mind when talking about setup and hold times.
The first is about violations - Suppose we have some setup time, say 7ns and we have 1ns setup violation. Does it mean that data arrives 6 ns before the clock edge or it means that data arrives 1ns after the edge?
And the second concerns hold times - what assures that my design has the required hold time. My opinion is that delays of an output signal of a stage with respect to the clock assure the hold time of the next one, for the next clock edge. Is this correct?

The answer is 6ns before the clock edge. If it 1ns after the clock edge, u r violating the hold time.
 

setup time and hold time

I also need the corresponding information!
 
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